Presentations

Cryptographic Contests

From C to Hardware: Toward Using High-Level Synthesis for Hardware Benchmarking of Candidates in Cryptographic Contests,
by Kris Gaj,
invited talk delivered at IRISA (Institute for Research in IT and Random Systems), Rennes, France, June 26, 2015.

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Battles of Cryptographic Algorithms: From AES to CAESAR in Software and Hardware,
by Kris Gaj,
keynote address delivered at the 5th Central Area Networking and Security Workshop, CANSec 2014, The University of Arkansas, Fayetteville, Arkansas, Apr. 4-5, 2014

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Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware,
by Kris Gaj,
keynote address delivered at the 14th Euromicro Conference on Digital System Design, DSD 2011, Oulu, Finland, Aug. 31-Sep. 2, 2011.

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CAESAR Contest

Toward Fair and Comprehensive Benchmarking of CAESAR Candidates in Hardware: Standard API, High-Speed ImplementaCons in VHDL/Verilog, and Benchmarking Using FPGAs,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Michael X. Lyons, Panasayya Yalla, and Kris Gaj,
presented at DIAC 2016, Nagoya, Japan, Sep. 25-27, 2016.

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Enhancing CAESAR Hardware API Support for Lightweight Architectures,
by Panasayya Yalla and Jens-Peter Kaps,
presented at DIAC 2016, Nagoya, Japan, Sep. 25-27, 2016.

abstract        slides

An Alternative Approach to Hardware Benchmarking of CAESAR Candidates Based on the Use of High-Level Synthesis Tools,
by Ekawat Homsirikamol and Kris Gaj,
presented at DIAC 2016, Nagoya, Japan, Sep. 25-27, 2016.

abstract        slides

Fair and Comprehensive Benchmarking of 29 Round 2 CAESAR Candidates in Hardware: Preliminary Results,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, and Kris Gaj,
presented at CryptArchi 2016, La Grande Motte, France, June 21-24, 2016.

abstract        slides

A Universal Hardware API for Authenticated Ciphers,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, and Kris Gaj
presented at ReConFig 2015, Mayan Riviera, Mexico, Dec. 7-9, 2015.

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GMU Hardware API for Authenticated Ciphers,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, and Kris Gaj
presented at DIAC 2015, Singapore, Sep. 27-29, 2015.

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C vs. VHDL: Benchmarking CAESAR Candidates Using High-Level Synthesis and Register-Transfer Level Methodologies,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, and Kris Gaj
presented at DIAC 2015, Singapore, Sep. 27-29, 2015.

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Toward a Universal High-Speed Interface for Authenticated Ciphers,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, and Kris Gaj
presented at CryptArchi 2015, Leuven, Belgium, June 28-July 1, 2015.

abstract        slides

C vs. VHDL: Comparing Performance of CAESAR Candidates Using High-Level Synthesis on Xilinx FPGAs,
by Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, and Kris Gaj
presented at CryptArchi 2015, Leuven, Belgium, June 28-July 1, 2015.

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Benchmarking of Cryptographic Algorithms in Hardware,
by Ekawat Homsirikamol and Kris Gaj
presented at DIAC 2014, Santa Barbara, USA, Aug. 23-24, 2014.

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SHA-3 Contest

Lightweight Implementations of SHA-3 Finalists on FPGAs,
by Jens-Peter Kaps, Panasayya Yalla, Kishore Kumar Surapathi, Bilal Habib, Susheel Vadlamudi, and Smriti Gurung
presented at the Third SHA-3 Candidate Conference, Washington, D.C., USA, Mar. 22-23, 2012.

slides       paper

Lessons Learned from Designing a 65 nm ASIC for Third Round SHA-3 Candidates,
by Frank K. Gurkaynak, Kris Gaj, Beat Muheim, Ekawat Homsirikamol, Christoph Keller, Marcin Rogawski, Hubert Kaeslin, Jens-Peter Kaps
presented at the Third SHA-3 Candidate Conference, Washington, D.C., USA, Mar. 22-23, 2012.

slides       paper

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs,
by Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj
presented at the Third SHA-3 Candidate Conference, Washington, D.C., USA, Mar. 22-23, 2012.

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Use of Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3 Candidates,
by Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, and Kris Gaj,
presented at 2011 International Conference on Field Programmable Technology - FPT 2011, New Delhi, India, Dec. 12-14, 2011.

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Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs,
by Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj
presented at CHES 2011, Nara, Japan, Sep. 28-Oct. 1, 2011.

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Investigating Design Space of Five Final SHA-3 Candidates in High-Performance FPGAs,
by Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski,
presented at CryptArchi 2011, Bochum, Germany, June 15-18, 2011.

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Comparing Hardware Performance of SHA-3 Candidates Using FPGAs,
by Kris Gaj
presented at the 2011 Quo Vadis Cryptology workshop, Warsaw, Poland, May 23-24, 2011.

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Comprehensive Comparison of Hardware Performance of Fourteen Round 2 SHA-3 Candidates with 512-bit Outputs Using Field Programmable Gate Arrays,
by Kris Gaj, Ekawat Homsirikamol, and Marcin Rogawski
presented at the Second SHA-3 Candidate Conference, Santa Barbara, CA, USA, Aug. 23-24, 2010.

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Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates using FPGAs,
by Kris Gaj, Ekawat Homsirikamol, and Marcin Rogawski
presented at CHES 2010, Santa Barbara, CA, USA, Aug. 17-20, 2010.

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ATHENa Tool

Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules,
by Benjamin Brewster, Ekawat Homsirikamol, Rajesh Velegalati, and Kris Gaj
presented at the 2012 International Conference on Field Programmable Technology, FPT 2012, Seoul, Korea, Dec. 2012.

poster

ATHENa 2.0 and ATHENa Database of Results
by Kris Gaj, Jens-Peter Kaps, Benjamin Y. Brewster, John Pham, Ekawat Homsirikamol, and Rajesh Velegalati
presented at presented at CryptArchi 2012, St-Etienne Goutelas, France, June 19-22, 2012.

abstract        slides

ATHENa: Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs,
by Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster,
presented at the 20th International Conference on Field Programmable Logic and Applications, FPL 2010, Milano, ITALY, Aug. 31st - Sep. 2nd, 2010.

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ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs
by Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster, John Pham, and Michal Varchola,
presented at CryptArchi 2010, Gif-sur-Yvette, France, June 27-30, 2010.

abstract        slides

Fair Comparison of Hardware Implementations of Cryptography without Revealing the Source Codes
by Kris Gaj, Venkata Amirineni, Ekwata Homsirikamol, Marcin Rogawski, Rajesh Velegalati, and Michal Varchola
presented at CryptArchi 2009, Prague, June 24-27, 2009.

abstract        slides

ATHENa – Automated Tool for Hardware EvaluatioN
by Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Ekawat Homsirikamol, Marcin Rogawski, and Rajesh Velegalati, George Mason University, USA,
Michal Varchola, Technical University of Kosice, Slovakia
poster presented at CHES 2009, Lausanne, Sep. 6-9, 2009.

poster

Benchmarking of Cryptographic Hardware
by Kris Gaj
presentation from the special session at CHES 2009 on Cryptographic Hardware Benchmarking moderated by Patrick Schaumont.

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