This page will contain proposals and critiques of proposals for interfaces of hardware cryptographic modules, such as hash functions, secret-key block ciphers, secret-key stream ciphers, message authentication codes, public-key ciphers, public-key signatures schemes, etc.
The proposed GMU interface for hash function modules has been described
as a part of the following publication:
E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptology ePrint Archive: Report 2010/445, first version - Aug. 2010. See Section 2.3 Uniform Interface.
An earlier version of the GMU proposal is available below:
Hardware Interface of a Secure Hash Algorithm (SHA) - v. 1.4 January 29, 2010.
interfaces for hash modules proposed by other groups are listed below:
B. Baldwin, A. Byrne, L. Lu, M. Hamilton, N. Hanley, M. O'Neill, and W. P. Marnane, A Hardware Wrapper for the SHA-3 Hash Algorithms, Cryptology ePrint Archive: Report 2010/124.
Z. Chen, S. Morozov, P. Schaumont, A Hardware Interface for Hashing Algorithms, Cryptology ePrint Archive: Report 2008/529.