Authenticated Encryption FPGA Ranking

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Result Filtering
    • CAESAR Round 3
    • CAESAR Round 3 (Round 2 variant)
    • CAESAR Round 2
    • CAESAR Round 1
    • Standards
    • Register Transfer Level
    • High Level Synthesis
    • Any
    • CAESAR Hardware API v1
    • GMU_AEAD_Core_API_v1
    • GMU_AEAD_Core_API_v0
    • Full-Block width (custom)
    • From To
    • Any

    • Without Embedded Resources (Block Memories, DSP Units, etc.)
    • Without Primitives or Megafunctions
    • LUTs
    • Slices
    • ALUTs
    • LEs
    • ALMs
    • Authenticated Encryption
    • Authenticated Decryption
    • Authentication Only
    • Throughput/Area
    • Throughput
    • Area


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Result ID Algorithm Key Size [bits] Impl Approach Hardware API Arch Type Primary Opt Target (Auth-Only TP)/ALM [(Mbits/s)/ALM] (Auth-Only TP)/LE [(Mbits/s)/LE] (Auth-Only TP)/ALUT [(Mbits/s)/ALUT] (Auth-Only TP)/Slice [(Mbits/s)/Slice] (Auth-Only TP)/LUT [(Mbits/s)/LUT] (Dec/Auth TP)/ALM [(Mbits/s)/ALM] (Dec/Auth TP)/LE [(Mbits/s)/LE] (Dec/Auth TP)/ALUT [(Mbits/s)/ALUT] (Dec/Auth TP)/Slice [(Mbits/s)/Slice] (Dec/Auth TP)/LUT [(Mbits/s)/LUT] (Enc/Auth TP)/ALM [(Mbits/s)/ALM] (Enc/Auth TP)/LE [(Mbits/s)/LE] (Enc/Auth TP)/ALUT [(Mbits/s)/ALUT] (Enc/Auth TP)/Slice [(Mbits/s)/Slice] (Enc/Auth TP)/LUT [(Mbits/s)/LUT] Auth-Only TP [Mbits/s] Enc/Auth TP [Mbits/s] Dec/Auth TP [Mbits/s] Impl Freq [MHz] ALMs LEs ALUTs LUTs CLB Slices BRAMs Memory Bits DSPs MULTs Primary Designer Affiliation Primary Designer Name(s) Family Group Megafunctions or Primitives