Post-Quantum Cryptography in Hardware and Embedded Systems

 

Reports on Benchmarking of Round 3 Candidates


 

Reports on Benchmarking of Round 2 Candidates


 

General Resources for All Rounds

Related Presentations:

GMU Source Code of PQC Algorithms:

High-Performance Hardware Implementation of CRYSTALS-Dilithium : based on the specifications available at the NIST PQC Round 3 Submissions page
v1.0, released in Dec. 2021
documented in the Cryptology ePrint Archive: Report 2022/217
"High-Performance Hardware Implementation of Lattice-Based Digital Signatures,"
by Luke Beckwith, Duc Tri Nguyen, and Kris Gaj.

PQC_NEON: NEON implementation of NIST PQC KEM finalists: CRYSTALS-Kyber, Saber, and NTRU : based on the specifications available at the NIST PQC Round 3 Submissions page
released in Apr. 2021
documented in the PQCrypto 2021 paper "Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists,"
by Duc Tri Nguyen and Kris Gaj.

Round 1 NIST PQC Candidates: NTRUEncrypt, NTRU-HRSS, NTRU Prime (Streamlined NTRU Prime and NTRU LPRime) : based on the specifications available at the NIST PQC Round 1 Submissions page
v1.0, released on May 8, 2019
documented in the PQCrypto 2019 paper
"Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign,"
by Farnoud Farahmand, Viet B. Dang, Duc Tri Nguyen, and Kris Gaj.

NTRUEncrypt SVES : based on the IEEE Standard Specification for Public Key Cryptographic Techniques Based on Hard Problems over Lattices, P1363.1-2008
v2.0, released on March 29, 2019
documented in the Cryptology ePrint Archive Report 2019/322
"A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES,"
by Farnoud Farahmand, Malik Umar Sharif, Kevin Briggs, and Kris Gaj.

Benchmarking Setup for Software/Hardware Implementations of PQC Schemes:

The proposed experimental setup is based on Xilinx Zynq UltraScale+ MPSoC, mounted on the ZCU104 or ZCU102 Evaluation Kit from Xilinx. This MPSoC is composed of two major parts, sharing the same chip, the Processing System (PS) and the Programmable Logic (PL). The PS includes a quad-core ARM Cortex-A53 Application Processing Unit (APU), out of which, we use only one processor (Core 0 of Cortex-A53), running at the frequency of 1.2GHz. The PL includes programmable FPGA fabric, similar to that of Virtex UltraScale+ FPGAs. The software used is Xilinx Vivado Design Suite HLx Edition and Xilinx Software Development Kit (XSDK), both with the versions no. 2018.2.

Related Publications:

  1. L. Beckwith, D.T. Nguyen, and K. Gaj, "High-Performance Hardware Implementation of CRYSTALS-Dilithium," in 2021 International Conference on Field-Programmable Technology, FPT 2021, Dec. 2021. (accepted version).
  2. A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj, "A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks," in 22nd International Conference on Cryptology in India, Indocrypt 2021, Jaipur, India, Dec. 2021. (accepted version).
  3. D.T. Nguyen and K. Gaj, "Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists," in 12th International Conference on Post-Quantum Cryptography, PQCrypto 2021, Springer, LNCS 12841, pp. 234-254, July 2021. (accepted version + slides short + slides long).
  4. D.T. Nguyen, V.B. Dang, and K. Gaj, "High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-based Post-Quantum Cryptography using Software/Hardware Codesign", in 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, LNCS 12083, pp. 247-257 (accepted version).
  5. V.B. Dang, F. Farahmand, M. Andrzejczak, and K. Gaj, "Implementing and Benchmarking Three Lattice-based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign", in 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, Dec. 11-13, 2019, pp. 206-214 (accepted version + slides).
  6. F. Farahmand, V. Dang, M. Andrzejczak, K. Gaj, "Implementing and Benchmarking Seven Round 2 Lattice-Based Key Encapsulation Mechanisms Using a Software/Hardware Codesign Approach," presented at the NIST Second PQC Standardization Conference, Santa Barbara, CA, USA, Aug. 22-24, 2019 (slides).
  7. M.X. Lyons and K. Gaj, "Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography", in 23rd Design, Automation and Test in Europe Conference, DATE 2020 (accepted version).
  8. D.T. Nguyen, V.B. Dang, and K. Gaj, "A High-Level Synthesis Approach to the Software/Hardware Codesign of NTT-based Post-Quantum Cryptography Algorithms", in 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, Dec. 11-13, 2019, pp. 371-374 (accepted version + poster).
  9. F. Farahmand, D. Nguyen, V. Dang, A. Ferozpuri, and K. Gaj, "Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies", in 29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, Sep. 9-13, 2019 (accepted version + poster).
  10. F. Farahmand, V. Dang, D. Nguyen, and K. Gaj, "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign," in J. Ding and R. Steinwandt (eds), 10th International Conference on Post-Quantum Cryptography, PQCrypto 2019, Chongqing, China, May 8-10, 2019, Lecture Notes in Computer Science, vol. 11505, Springer, pp. 23-43 (paper + slides).
  11. F. Farahmand, M. U. Sharif, K. Briggs, and K. Gaj, "A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES," in 2018 International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, Dec. 10-14, 2018 (extended ePrint version + accepted version + slides).

NIST Websites: