Post-Quantum Cryptography

Report on Hardware and Software/Hardware Benchmarking:

"Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches,"
by Viet Ba Dang, Farnoud Farahmand, Michal Andrzejczak, Kamyar Mohajerani, Duc Tri Nguyen, and Kris Gaj
First posted on: June 2, 2020; Last updated: October 13, 2020

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Related Presentations:

  • Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using FPGAs,
    presentation by Kris Gaj, NIST Round 3 Seminars, October 27, 2020.

  • Benchmarking Setup for Software/Hardware Implementations of PQC Schemes:

    The proposed experimental setup is based on Xilinx Zynq UltraScale+ MPSoC, mounted on the ZCU104 or ZCU102 Evaluation Kit from Xilinx. This MPSoC is composed of two major parts, sharing the same chip, the Processing System (PS) and the Programmable Logic (PL). The PS includes a quad-core ARM Cortex-A53 Application Processing Unit (APU), out of which, we use only one processor (Core 0 of Cortex-A53), running at the frequency of 1.2GHz. The PL includes programmable FPGA fabric, similar to that of Virtex UltraScale+ FPGAs. The software used is Xilinx Vivado Design Suite HLx Edition and Xilinx Software Development Kit (XSDK), both with the versions no. 2018.2.

    GMU Source Code of PQC Algorithms:

    Round 1 NIST PQC Candidates: NTRUEncrypt, NTRU-HRSS, NTRU Prime (Streamlined NTRU Prime and NTRU LPRime) : based on the specifications available at the NIST PQC Round 1 Submissions page
    v1.0, released on May 8, 2019
    documented in the PQCrypto 2019 paper
    "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign,"
    by Farnoud Farahmand, Viet B. Dang, Duc Tri Nguyen, and Kris Gaj.

    NTRUEncrypt SVES : based on the IEEE Standard Specification for Public Key Cryptographic Techniques Based on Hard Problems over Lattices, P1363.1-2008
    v2.0, released on March 29, 2019
    documented in the Cryptology ePrint Archive Report 2019/322
    "A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES,"
    by Farnoud Farahmand, Malik Umar Sharif, Kevin Briggs, and Kris Gaj.

    Hardware API:

    Hardware API for Post-Quantum Public Key Cryptosystems, full specification, v2.0, last revised April 10, 2018.
    [history of updates, previous versions]

    Related Publications:

    1. F. Farahmand, V. Dang, M. Andrzejczak, K. Gaj, "Implementing and Benchmarking Seven Round 2 Lattice-Based Key Encapsulation Mechanisms Using a Software/Hardware Codesign Approach," presented at the NIST Second PQC Standardization Conference, Santa Barbara, CA, USA, Aug. 22-24, 2019 (slides).
    2. V.B. Dang, F. Farahmand, M. Andrzejczak, and K. Gaj, "Implementing and Benchmarking Three Lattice-based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign", in 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, Dec. 11-13, 2019, pp. 206-214 (accepted version + slides).
    3. M.X. Lyons and K. Gaj, "Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography", in 23rd Design, Automation and Test in Europe Conference, DATE 2020 (accepted version).
    4. D.T. Nguyen, V.B. Dang, and K. Gaj, "High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-based Post-Quantum Cryptography using Software/Hardware Codesign", in 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, LNCS 12083, pp. 247-257 (accepted version).
    5. D.T. Nguyen, V.B. Dang, and K. Gaj, "A High-Level Synthesis Approach to the Software/Hardware Codesign of NTT-based Post-Quantum Cryptography Algorithms", in 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, Dec. 11-13, 2019, pp. 371-374 (accepted version + poster).
    6. F. Farahmand, D. Nguyen, V. Dang, A. Ferozpuri, and K. Gaj, "Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies", in 29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, Sep. 9-13, 2019 (accepted version + poster).
    7. F. Farahmand, V. Dang, D. Nguyen, and K. Gaj, "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign," in J. Ding and R. Steinwandt (eds), 10th International Conference on Post-Quantum Cryptography, PQCrypto 2019, Chongqing, China, May 8-10, 2019, Lecture Notes in Computer Science, vol. 11505, Springer, pp. 23-43 (paper + slides).
    8. F. Farahmand, M. U. Sharif, K. Briggs, and K. Gaj, "A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES," in 2018 International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, Dec. 10-14, 2018 (extended ePrint version + accepted version + slides).