Database of FPGA Results for Authenticated Ciphers

Show Help

Compare Selected

Result ID Group Algorithm Design ID Src Avail Device Vendor Family Enc/Auth TP [Mbits/s] Dec/Auth TP [Mbits/s] Auth-Only TP [Mbits/s] Synth Freq [MHz] Key Sched Time [ns] Impl Freq [MHz] (Enc/Auth TP)/Slice [(Mbits/s)/Slice] (Dec/Auth TP)/Slice [(Mbits/s)/Slice] (Auth-Only TP)/Slice [(Mbits/s)/Slice] (Enc/Auth TP)/LE [(Mbits/s)/LE] (Dec/Auth TP)/LE [(Mbits/s)/LE] (Auth-Only TP)/LE [(Mbits/s)/LE] (Enc/Auth TP)/ALUT [(Mbits/s)/ALUT] (Enc/Auth TP)/ALM [(Mbits/s)/ALM] (Dec/Auth TP)/ALM [(Mbits/s)/ALM] (Dec/Auth TP)/ALUT [(Mbits/s)/ALUT] (Auth-Only TP)/ALM [(Mbits/s)/ALM] (Auth-Only TP)/ALUT [(Mbits/s)/ALUT] CLB Slices LEs ALUTs ALMs LUTs Flip Flops MULTs DSPs BRAMs Memory Bits Estimated Power [mW] Estimated Energy/Bit [mJ/Gbit] Measured Power [mW] Measured Energy/Bit [mJ/Gbit] HLS Tool HLS Tool Input Lang HLS Tool Output Lang HLS Tool Version HLS Tool Options Synth Tool Synth Tool Version Impl Tool Impl Tool Ver Primary Designer Name(s) Primary Designer Affiliation Result Modify Date Design Entered By