Database of FPGA Results for Authenticated Ciphers

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Result ID Group Algorithm Key Size [bits] Assoc Data Secret Message # Secret Message # Size [bits] Msg Blk Size [bits] Design ID Impl Approach Hardware API ceil(log2(Max Len)) Primary Opt Target Secondary Opt Target Arch Type Language Megafunctions or Primitives Max #Streams Clk Cycles per Block (Long Msg) Datapath Width [bits] Padding Input Bus Width [bits] Key Sched Time Formula Enc/Auth Time Formula Dec/Auth Time Formula Auth-Only Time Formula Interface/Protocol Spec Src Avail Device Vendor Family LUTs CLB Slices ALUTs LEs ALMs Flip Flops MULTs DSPs BRAMs Memory Bits Impl Freq [MHz] Enc/Auth TP [Mbits/s] Dec/Auth TP [Mbits/s] Auth-Only TP [Mbits/s] Synth Freq [MHz] Key Sched Time [ns] (Enc/Auth TP)/Slice [(Mbits/s)/Slice] (Enc/Auth TP)/LUT [(Mbits/s)/LUT] (Dec/Auth TP)/Slice [(Mbits/s)/Slice] (Dec/Auth TP)/LUT [(Mbits/s)/LUT] (Auth-Only TP)/LUT [(Mbits/s)/LUT] (Auth-Only TP)/Slice [(Mbits/s)/Slice] (Enc/Auth TP)/LE [(Mbits/s)/LE] (Dec/Auth TP)/LE [(Mbits/s)/LE] (Auth-Only TP)/LE [(Mbits/s)/LE] (Enc/Auth TP)/ALUT [(Mbits/s)/ALUT] (Enc/Auth TP)/ALM [(Mbits/s)/ALM] (Dec/Auth TP)/ALM [(Mbits/s)/ALM] (Dec/Auth TP)/ALUT [(Mbits/s)/ALUT] (Auth-Only TP)/ALM [(Mbits/s)/ALM] (Auth-Only TP)/ALUT [(Mbits/s)/ALUT] Estimated Power [mW] Estimated Energy/Bit [mJ/Gbit] Measured Power [mW] Measured Energy/Bit [mJ/Gbit] HLS Tool HLS Tool Input Lang HLS Tool Output Lang HLS Tool Version HLS Tool Options Synth Tool Synth Tool Version Impl Tool Impl Tool Ver Primary Designer Name(s) Primary Designer Affiliation Result Modify Date Design Entered By