P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wójcik, "ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption," in LNCS 8731, Cryptographic Hardware and Embedded Systems - CHES 2014, Busan, South Korea, Sep. 23-26, 2014 (slides + ePrint version).
E. Homsirikamol and K. Gaj, "Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study," in LNCS 9040, 11th International Symposium on Applied Reconfigurable Computing, ARC 2015, Bochum, Apr. 13-17, 2015, pp. 217-228.
K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, "Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs," Cryptology ePrint Archive: Report 2012/368, first version - June 2012, final version - October 2012 (report).
E. Homsirikamol, M. Rogawski, and K. Gaj, "Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs," in LNCS 6917, Cryptographic Hardware and Embedded Systems - CHES 2011, Nara, Japan, Sep. 28-Oct. 1, pp. 491-506 (slides + accepted version)
R. Shahid, U. Sharif, M. Rogawski, and K. Gaj, "Use of Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3 Candidates," in 2011 International Conference on Field Programmable Technology - FPT 2011, New Delhi, India, Dec. 2011. (slides + accepted version)
E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptology ePrint Archive: Report 2010/445, first version - Aug. 2010 (report).
K. Gaj, E. Homsirikamol, and M. Rogawski, “Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,” in LNCS 6225, Cryptographic Hardware and Embedded Systems - CHES 2010, Santa Barbara, CA, USA, Aug. 2010, pp. 264-278 (slides + accepted version).
D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj, "Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates," Proc. State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pp. 151-162, Feb. 2008. (paper + slides)
K. Gaj, G. Southern and R. Bachimanchi, "Comparison of Hardware
Performance of Selected Phase 2 eSTREAM Candidates," Proc. SASC 2007:
Stream Ciphers Revisited, ECRYPT eSTREAM workshop, Bochum, Germany,
Jan. 31-Feb. 1, 2007. (paper + slides)
The eSTREAM Project: Hardware Performance Evaluations
K. Gaj and P. Chodowiec, "Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard using Field Programmable Gate Arrays," LNCS 2020, Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA Conference 2001 - Cryptographers' Track, San Francisco, Apr. 2001, pp. 84-99. (paper + slides)
K. Gaj and P. Chodowiec, "Hardware performance of the AES finalists - survey and analysis of results," Technical Report, George Mason University, Sep. 2000. (report)
K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," Proc. 3rd Advanced Encryption Standard Conference, New York, April 2000, pp. 40-54. (paper + slides)