ATHENa

GMU Source Code

Introduction

The source code provided below has been generated by members of the Cryptographic Engineering Research Group (CERG) at George Mason University in the period from October 1, 2014 to present.

GMU Source Code

Introduction

Source Code for CAESAR Round 3 Candidates (RTL VHDL, High-Speed Implementations)

Source Code for CAESAR Round 3 Candidates (RTL VHDL, Lightweight Implementations)

Source Code for CAESAR Round 3 Candidates (HLS-ready C and automatically generated RTL VHDL, High-Speed Implementations)

Source Code for CAESAR Round 2 Candidates (RTL VHDL, High-Speed Implementations)

Source Code for AES-GCM (RTL VHDL)

Source Code for AES (RTL VHDL, High-Speed Implementation)

Source Code for AES (HLS-ready C and automatically generated RTL VHDL, Verilog, and SystemC, High-Speed Implementation)

Source Code for the Keccak Permutation F (RTL VHDL, High-Speed Implementation)

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