History of Updates

• v1.1-1 : July 18, 2016

• Minor changes required to support correct simulation using ModelSim.

• v1.1 : July 9, 2016

• Support for two different architectures
  v1-1: Single-round iterative architecture, with one round per clock cycle, and
  v1-2: x2 Unrolled architecture, with two rounds (one step) per clock cycle.
  Source code for these two architectures is located in separate folders: src_rtl/v1-1 and src_rtl_v1-2.
• Corrected headers of the test vector files located in the folder KAT.

• v1.0 : Initial release : June 30, 2016

• Support for a single architecture.
  v1: x2 Unrolled architecture, with two rounds (one step) per clock cycle.