FPGA Hash Function Results Table

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Result ID Group Algorithm Hash Size [bits] Msg Blk Size [bits] Design ID Primary Opt Target Secondary Opt Target Arch Type Language Megafunctions or Primitives Max #Streams Clk Cycles per Block Datapath Width [bits] Padding Input Bus Width [bits] Src Avail Device Vendor Family TP [Mbits/s] Synth Freq [MHz] Impl Freq [MHz] TP/ALUTs [(Mbits/s)/ALUTs] TP/LEs [(Mbits/s)/LEs] TP/CLB Slices [(Mbits/s)/CLB Slices] CLB Slices LEs ALUTs LUTs Flip Flops MULTs DSPs BRAMs Memory Bits Estimated Power [mW] Estimated Energy/Bit [mJ/Gbit] Measured Power [mW] Measured Energy/Bit [mJ/Gbit] Synth Tool Synth Tool Version Impl Tool Impl Tool Ver Primary Designer Name(s) Primary Designer Affiliation Result Modify Date Design Entered By