Post-Quantum Cryptography in Hardware and Embedded Systems

Post-Quantum Cryptography

Major investment by companies, such as Google, IBM, Intel, Microsoft, and NTT, has led to the first general-purpose quantum processors, and selecting quantum computing as one of the ten breakthrough technologies of 2017. The goal of this project is to support NIST in its effort to develop a new generation of public-key cryptographic standards, resistant against quantum computers, a.k.a. NIST Post-Quantum Cryptography (PQC) Standardization Process. In Round 1 of this effort, the assessment of PQC candidates has focused primarily on their security and software efficiency. Relatively little progress has been made so far to understand the true potential of these algorithms for efficient and secure hardware and embedded systems implementations. The goal of this project is to set the foundation for the early, systematic, and comprehensive study of the hardware efficiency of the most promising PQC candidates, through the definition of the universal PQC Hardware API, generation of the universal Development Package, and employment of novel methodologies such as Software/Hardware Codesign and High-Level Synthesis. The next 5-10 years are very likely to bring the biggest revolution in cryptography, since the invention of public-key cryptography in mid-1970s. This project gives us a unique opportunity to influence the choice of future cryptographic standards, which are likely to be developed and deployed within the next decade and remain in use for the significant portion (if not the rest) of the 21st century.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Job Announcements:

GRA Positions in Post-Quantum Cryptography

CERG is seeking qualified candidates for multiple Graduate Research Assistant positions in the area of efficient implementations of Post-Quantum Cryptosystems, side-channel attacks targeting these cryptosystems, and countermeasures against such attacks. The desired qualifications include strong mathematical background in algebra and number theory, experience in hardware design using hardware description languages, and knowledge of C and scripting languages, such as Python. Additional experience in Magma or SageMath, ASIC or FPGA design, software/hardware codesign, High-Level Synthesis, embedded software development, and Linux operating system is a plus.

GRA Position in Lightweight Cryptography

CERG is seeking qualified candidates for a Graduate Research Assistant position in the area of efficient and secure implementations of Lightweight Cryptography. The desired qualifications include experience in embedded systems, knowledge of C, assembly and scripting languages, hardware design using hardware description languages, Linux operating system, and strong experimental skills. Additional experience in side-channel and fault attacks, countermeasures against these attacks, ASIC or FPGA design, software/hardware codesign, embedded software development, and/or circuit/PCB design is a plus.

All positions are open starting in August 2019 or January 2020. Qualified candidates should apply to the ECE PhD program at George Mason University, indicating Dr. Gaj and/or Dr. Kaps as possible future advisors. In parallel, an earlier e-mail contact with Dr. Gaj and/or Dr. Kaps is highly recommended.


Latest News:

Dr. Gaj and Michal Andrzejczak will give talks at CryptArchi 2019

Dr. Gaj and Michal Andrzejczak will attend the 17th International Workshop on Cryptographic Architectures Embedded in Logic Devices, CryptArchi 2019, held in Pruhonice near Prague, Czech Republic, on June 23-26, 2019. Dr. Gaj will give a talk entitled "Toward Efficient and Fair Software/Hardware Codesign and Benchmarking of Candidates in Round 2 of the NIST PQC Standardization Process," and Michal Andrzejczak will deliver a presentation entitled "Lattice sieving acceleration in FPGAs". (06/08/2019)


Dr. Kaps gave a talk at NIST

On June 4, 2019, Dr. Kaps met with members of the Cryptographic Technology Group at NIST, on the NIST campus in Gaithersburg, MD, gave a presentation entitled "Lightweight Cryptography in Hardware and Embedded Systems," and discussed the status of the NIST Lightweight Cryptography standardization process. (06/05/2019)


Farnoud Farahmand presented a poster at the DAC 2019 Work-in-Progress Session

Farnoud Farahmand attended the Design Automation Conference, DAC 2019, held in Las Vegas, NV, on June 2-6, 2019. He presented a poster in the DAC 2019 Work-in-Progress Session, entitled "Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies," based on his joint work with Duc Tri Nguyen, Viet Ba Dang, Ahmed Ferozpuri, and Kris Gaj. (06/07/2019)


Ted Winograd gave a talk at RAW 2019

Ted Winograd attended the 26th Reconfigurable Architectures Workshop, RAW 2019, held in Rio de Janeiro, Brazil, on May 20, 2019. Ted gave an oral presentation entitled "An Automated Scheduler-based Approach for the Development of Cryptoprocessors for Pairing-Based Cryptosystems," based on the paper co-authored with Rabia Shahid and Kris Gaj. (05/21/2019)


Farnoud Farahmand's internship at Google

Farnoud Farahmand has qualified for an internship at Google in Mountain View, CA, to be conducted in Summer and Fall 2019. (05/20/2019)


Dr. Gaj gave talks at the Fudan and Shanghai Jiao Tong universities in Shanghai, China

Dr. Gaj visited the Cryptography and Information Security Lab at Fudan University in Shanghai, China, on May 16, 2019. One of his hosts, Dr. Yunlei Zhao, is a primary designer of one of the candidates in the NIST Post-Quantum Cryptography standardization process KCL - Key Consensus from Lattice. His other hosts included Dr. Yiming Zhao and Dr. Yuedong Xu. Dr. Gaj gave two presentations entitled "From AES to Post-Quantum & Lightweight Cryptography: Battles of Cryptographic Algorithms in Hardware" and "Post-Quantum Cryptography in Hardware and Embedded Systems: Toward Choosing the Most Efficient and Flexible New Public Key Cryptography Standards". The following day, on May 17, 2019, Dr. Gaj visited the Lab of Cryptology and Computer Security in the Department of Computer Science and Engineering, at Shanghai Jiao Tong University (SJTU). His hosts at SJTU included Dr. Lei Wang, Dr. Zhiqiang Liu, and Dr. Dawu Gu. Dr. Wang is the designer of SHELL - an authenticated cipher which competed in the CAESAR contest. At SJTU, Dr. Gaj gave a talk entitled "Battles of Cryptographic Algorithms in Hardware and Software: Toward Choosing the Most Efficient and Flexible Post-Quantum Cryptography Standard". (05/18/2019).


Michael Tempelmeier from TUM, Germany, visited CERG

On May 10, 2019, CERG hosted Michael Tempelmeier from Technical University of Munich (TUM) in Germany. Michael gave a talk entitled "Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography," based on his joint work with Tim Fritzmann and Dr. Johanna Sepulveda. He also gave a presentation entitled "Using Hardware Software Codesign for Optimized Implementations of High-Speed and Defense in Depth CEASAR Finalists". Short talks were given by Dr. William Diehl, and several members of CERG, including Dr. Kaps, Farnoud Farahmand, Viet Ba Dang, Duc Tri Nguyen and Kamyar Mohajerani. (05/11/2019)


Dr. Gaj gave a talk at PQCrypto 2019

Dr. Gaj attended the 10th International Conference on Post-Quantum Cryptography, PQCrypto 2019, held in Chongqing, China, on May 8-10, 2019. Dr. Gaj gave an oral presentation entitled "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign," based on the paper co-authored with Farnoud Farahmand, Viet Ba Dang, and Duc Tri Nguyen. Before the main conference, Dr. Gaj also attended the half-day Summer School on Post-Quantum Cryptography, including lectures by Drs. Daniel Smith-Tone, Nicolas Sendrier, and Jean-Francois Biasse. (05/11/2019)


CERG students attended HOST tutorials

Several members of CERG, including Abubakr Abdulgadir, Viet Ba Dang, Farnoud Farahmand, Michael X. Lyons, Kamyar Mohajerani, and Duc Tri Nguyen, as well as the visiting student Michal Andrzejczak, attended tutorials at the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, held on May 6, 2019. (05/07/2019)


CERG at the NIST PQC Hardware Day

Several members of CERG, including Dr. Gaj, Dr. Kaps, Abubakr Abdulgadir, Viet Ba Dang, Ahmed Ferozpuri, Michael X. Lyons, and Duc Tri Nguyen, as well as the visiting student Michal Andrzejczak, attended the NIST PQC Hardware Day, held on the NIST campus in Gaithersburg, MD, on May 2, 2019. Dr. Gaj gave a presentation entitled "Hardware and Software/Hardware Benchmarking of PQC Schemes" and Dr. Kaps delivered a talk "Evaluation of PQC Candidates using FOBOS and XXBX". Other speakers of the NIST PQC Hardware Day included Dr. Dustin Moody from NIST, Dr. Reza Azarderakhsh from Florida Atlantic University, Dr. James Howe from the University of Bristol, UK, Matthias Kannwischer from the Radboud University Nijmegen, the Netherlands, and Dr. Kanad Basu from the New York University. (05/03/2019)


Farnoud Farahmand defended his Ph.D. Thesis Proposal

Farnoud Farahmand defended his PhD Thesis Proposal, entitled "Comprehensive Hardware Evaluation of Cryptographic Algorithms from Authenticated Ciphers to Post-Quantum Cryptography: Implementation Methods, Benchmarking Platforms, Analysis Tools, and Resistance to Side-Channel Attacks," on April 8, 2019. Members of his dissertation committee include Dr. Gaj (Chair), Dr. Diehl, Dr. Kaps, and Dr. Sasan. (04/09/2019)


Visiting student from the Military University of Technology in Warsaw

In the period from January 22 to May 24, 2019, CERG is hosting Michal Andrzejczak, a Ph.D. student from the Institute of Mathematics and Cryptology in the Faculty of Cybernetics at the Military University of Technology in Warsaw, Poland. Michal's research interests include hardware implementations of Post-Quantum Cryptography (PQC) algorithms and methods of breaking them. In particular, his Ph.D. research involves the implementation of the NIST PQC candidate Round5, as well as the lattice sieving algorithms, which are believed to be the most efficient known algorithms for solving the shortest vector problem (SVP) in lattices. SVP is one of the primary hard mathematical problems underlying the security of lattice-based PQC schemes. (02/01/2019)


CERG paper accepted to PQCrypto 2019

The CERG paper entitled "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign," co-authored by Farnoud Farahmand, Viet B. Dang, Duc Tri Nguyen, and Kris Gaj has been accepted for an oral presentation at the Tenth International Conference on Post-Quantum Cryptography, PQCrypto 2019, to be held at the Chongqing University, in Chongqing, China, on May 8-10, 2019. (01/13/2019)


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • T. Winograd, R. Shahid, and K. Gaj, An automated scheduler-based approach for the development of cryptoprocessors for pairing-based cryptosystems, 26th Reconfigurable Architectures Workshop, RAW 2019, Rio de Janeiro, Brazil, May, 2019 [Bibtex]
  • F. Farahmand, V.B. Dang, D.T. Nguyen, and K. Gaj, Evaluating the potential for hardware acceleration of four NTRU-based Key Encapsulation Mechanisms using software/hardware codesign, 10th International Conference on Post-Quantum Cryptography, PQCrypto 2019, Chongqing, China, LNCS, Springer, May, 2019 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the caesar lightweight finalists: Acorn vs. Ascon, Cryptology ePrint Archive, number 2019, pages 184, March, 2019 [Bibtex]
  • F. Farahmand, M.U. Sharif, K. Briggs, and K. Gaj, A high-speed constant-time hardware implementation of NTRUEncrypt SVES, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • A. Ferozpuri and K. Gaj, High-speed FPGA implementation of the NIST Round 1 Rainbow signature scheme, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • M. Tempelmeier, J.-P. Kaps, and G. Sigl, Experimental power and performance evaluation of CAESAR hardware finalists, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • G. Banegas, P.S.L.M. Barreto, B.O. Boidje, P.-L. Cayrel, G.N. Dione, K. Gaj, C.T. Gueye, R. Haeussler, J.B. Klamti, O. Ndiaye, D.T. Nguyen, and E. Persichetti, DAGS: Key encapsulation using Dyadic GS codes, Journal of Mathematical Cryptology, volume 12, number 4, pages 221–240, December, 2018 [Bibtex]
  • K. Gaj, Challenges and rewards of implementing and benchmarking Post-Quantum Cryptography in hardware, The 28th ACM Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, ACM, May, 2018 [Bibtex]
  • F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Improved lightweight implementations of CAESAR authenticated ciphers, The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, IEEE, pages 29–36, April, 2018 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, The CAESAR-api in the real world - towards a fair evaluation of hardware CAESAR candidates, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, April, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Side-channel resistant soft core processor for lightweight block ciphers, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • F. Farahmand, A. Ferozpuri, W. Diehl, and K. Gaj, Minerva: Automated hardware optimization tool, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, IEEE, Dec., 2017 [Bibtex]
  • P. Yalla and J.-P. Kaps, Evaluation of CAESAR hardware API for lightweight implementations, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • A. Salman, W. Diehl, and J.-P. Kaps, A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • E. Homsirikamol and K. Gaj, Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, Dec, 2017 [Bibtex]
  • B. Jarvis and K. Gaj, Selection of an error-correcting code for FPGA-based Physical Unclonable Functions, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, IEEE, Dec., 2017 [Bibtex]
  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • S. Deshpande and K. Gaj, Analysis and inner-round pipelined implementation of selected parallelizable CAESAR competition candidates, 19th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, Aug., 2017 [Bibtex]
  • B. Habib, J.-P. Kaps, and K. Gaj, Implementation of efficient SR-latch PUF on FPGA and SoC devices, Microprocessors and Microsystems, volume 53, pages 92-105, Aug., 2017 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of selected CAESAR round two authenticated ciphers, Microprocessors and Microsystems, volume 52, pages 202-218, July, 2017 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Microprocessors and Microsystems, volume 51, pages 239-251, June, 2017 [Bibtex]
  • R. Shahid, T. Winograd, and K. Gaj, A generic approach to the development of coprocessors for Elliptic Curve Cryptosystems, 24th Reconfigurable Architectures Workshop, RAW 2017, Orlando, FL, May, 2017 [Bibtex]
  • C. Marchand, L. Bossuet, and K. Gaj, Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes, International Journal of Circuit Theory and Applications, volume 45, pages 274-291, Feb., 2017 [Bibtex]
  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]