CERG presents ATHENa

ATHENa

ATHENa: Automated Tool for Hardware EvaluatioN is a project started at George Mason University, aimed at fair, comprehensive, and automated evaluation of cryptographic cores developed using hardware description languages, such as VHDL and Verilog. Our environment, in its final version, will be based on a comprehensive set of scripts, to be downloaded freely from the project web site, and run on computers belonging to the authors of HDL codes. As main features our environment will run all steps of synthesis, implementation, and timing analysis in the batch mode and support devices and tools of the three major FPGA vendors: Xilinx, Altera, Actel.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.

Latest News:

CERG Announces the Release of ATHENa Version 0.3

CERG released version 0.3 of the Automated Tool for Hardware EvaluatioN (ATHENa) on 11/17/09. The main new features are the support for Altera FPGAs in addition to Xilinx FPGAs, exhaustive search for optimum options of synthesis and implementation tools and an enhanced error handling capability. In addition to the multiplier example, this release contains a VHDL implementation of SHA 256. The latest release can be donwloaded from the download section of the ATHENa webpage. (11/17/09)

Dr. Gaj and Dr. Kaps attend CHES 2009

Dr. Gaj and Dr. Kaps attended CHES 2009, held in Lausanne, Switzerland on September 6-9, 2009. Dr. Gaj has served as a Program Co-chair of this workshop, and he gave a part of the Welcome Talk summarizing interesting statistics about the workshop. He also presided together with Dr. Clavier and Dr. Kaihara over the Best Paper Award Ceremony, and the presentation of the Program Committee. Additionally, Dr. Gaj was an Invited Speaker at a special session devoted to Benchmarking of Cryptographic Hardware, chaired by Dr. Schaumont. Finally, the CERG poster entitled "ATHENa - Automated Tool for Hardware EvaluatioN" was presented by Dr. Gaj and Dr. Kaps during the workshop poster session. (9/25/09)

CERG welcomes new MS Student

Abirami Prabhakaran joined CERG in September 2009. She will be doing her MS Theses on Differential Power Analysis under the supervision of Dr. Kaps, with Dr. Gaj as member of her thesis committee. (9/25/09)

CERG welcomes Prof. Kwon

Prof. Soonhak Kwon is a visiting professor from Sungkyunkwan University in Suwon, Korea. He is a well-known expert in the area of algebra, number theory and hardware architectures for elliptic curve and pairing-based cryptosystems. He is joining CERG for the period from July 2009 to August 2010. This is his second stay at GMU, after his first sabbatical visit from July 2005 to August 2006. (9/12/09)

CERG welcomes Dr. Fernandez

Dr. Daniel Piso Fernandez is a post-doctoral research fellow, who completed his Ph.D. at in the Department of at Electronic and Computer Engineering at the University of Santiago de Compostela in Spain. His main research interests include computer arithmetic, computer architecture, parallel programming, and operating systems. He is joining CERG for the period from July 2009 to August 2010. This is his first visit at GMU.(9/12/09)

Dr. Gaj and Marcin Rogawski give talks at CryptArchi 2009

Dr. Gaj and Marcin Rogawski attended CryptArchi workshop held in Prague, Czech Republic, on June 24-27, 2009. Dr. Gaj gave a talk entitled "Fair Comparison of Hardware Implementations of Cryptography without Revealing the Source Codes" (Abstract) and Marcin Rogawski gave a talk on "Implementing SHA1 and SHA2 Standards on the Eve of SHA3 Competition" (Abstract). (9/12/09)

Dr. Gaj is a guest editor for Integration, the VLSI Journal

Dr Gaj. is a guest editor for Integration, the VLSI Journal - Special Issue "Hardware Architectures for Algebra, Cryptology and Number Theory". Please follow the link for the Call for Papers in HTML or the Call for Papers in PDF for more information on this upcoming special issue. The submission deadline for articles is July, 25th 2009. (3/07/09)

Dr. Kaps is a member of the Program Committee of Indocrypt 2009

Indocrypt 2009 is the 10th International Conference on Cryptology in India to be held in New Delhi, India, on December 13-16, 2009. (1/19/09)

Document Database Version 1.4 Released

Dr. Kaps of the Cryptographic Engineering Research Group (CERG) released version 1.4 of the Document Database software. It is used by our research lab (CERG) as well as other research groups world wide. The Document Database is a management system for published documents which enables groups of people, e.g. members of a research lab, to maintain an up-to-date repository of relevant documents and retrieve their BibTeX data. The main new feature of the new version 1.4 are user definable data fields, publicly accessible documents, improved foreign character support and a statistics page. The latest version can be downloaded from Sourceforge. (1/11/2009)

Dr. Gaj is currently serving as a Program Co-Chair of CHES 2009

CHES 2009 Workshop on Cryptographic Hardware and Embedded Systems is to be held in Lausanne, Switzerland on September 6-9, 2009. Dr. Kaps is a member of the Program Committee and the Web Master for the same workshop. CHES is sponsored by the IACR, the International Association for Cryptologic Research. (1/06/09)

Seminars:

Differential Power Analysis Attacks on Light Weight Implementations of Block Ciphers

Panasayya Yalla, MS CpE Master's Thesis Presentation
Date: Monday, July 27th, 2:00 pm, Location: Engineering Building, Room 3507

Abstract

There is a growing interest in light weight implementation of cryptographic algorithms for low-resource ubiquitous computing devices such as a wireless sensor nodes (WSN) or radio frequency identification (RFID) tags. Most light weight cryptographic implementations are targeted to application specific integrated circuits (ASIC). However, ASICs have a high non-recurring engineering cost and longer time to market. Even though field programmable gate arrays (FPGA) are reconfigurable and have low non-recurring engineering cost, they consume more power than ASICs. Power consumption is a primary concern for light weight cryptographic applications. With the development of low-cost, low-power FPGAs for battery powered devices, they are becoming an interesting target for light weight cryptography (LWC). Compact architectures of AES, Camellia, xTEA, HIGHT and Present are implemented on low-cost Xilinx Spartan3 FPGAs. Different optimization techniques are employed to minimize the area consumption by smart use of the Configurable Logic Block (CLB) structure in FPGAs. All the cipher implementations are light weight but with full strength security i.e. not 80-bit but 128-bit key length. Furthermore, differential power analysis (DPA) attacks are performed on these implementations to investigate their "natural", i.e. without any countermeasures resistance to this form of attack.

Securing Light Weight Cryptographic Implementations on FPGAs Using DPL

Rajesh Velegalati, MS CpE Master's Thesis Presentation
Date: Monday, July 27th, 4:00 pm, Location: Engineering Building, Room 3507

Abstract

Recent advances in Field Programmable Gate Array (FPGA) technology are bound to make FPGAs a popular platform for battery powered devices. Many applications of such devices are mission critical and require the use of cryptographic algorithms to provide the desired security. However, Differential Power Analysis (DPA) attacks pose a severe threat against otherwise secure cryptographic implementations.

Current techniques to defend against DPA attacks such as Dual rail with Pre-Charge Logic (DPL) lead to an increase in area consumption of factor 4 or more which is not suitable for Light Weight implementations. Current secure implementations using DPL require ASIC tools and a special ASIC library. In this thesis we show that moderate security against DPA attacks can be achieved for DPL secured implementations using only FPGA CAD tools augmented by some scripts. The resulting circuit has an area increase of not much more than a factor two over standard FPGA implementations. We demonstrate our approach by implementing a cryptographic algorithm on Spartan3E FPGA and assessing the security it provides against DPA. We also study one of the Xilinx FPGA specific intrinsic features - Wide Dedicated Multiplexer (WDM) - with respect to DPA.

Latest Publications:

  • P. Yalla and J.-P. Kaps, Lightweight cryptography for FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'09, IEEE, pages 225–230, Dec., 2009 [Bibtex]
  • Cryptographic hardware and embedded systems – CHES 2009, Lecture Notes in Computer Science , volume 5747 , Springer, Sep., 2009 [Bibtex]
  • C. Shu, S. Kwon, and K. Gaj, Reconfigurable computing approach for tate pairing cryptosystems over binary fields, IEEE Transactions on Computers, volume 58, pages 1221-1237, Sep., 2009 [Bibtex]
  • K. Gaj and P. Chodowiec, Cryptographic engineering, Springer, FPGA and ASIC Implementations of AES, pages 235-294, 2009 [Bibtex]
  • R. Velegalati and J.-P. Kaps, DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 385–390, Aug, 2009 [Bibtex]
  • P. Yalla and J.-P. Kaps, Compact FPGA implementation of Camellia, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 658–661, Aug., 2009 [Bibtex]