Welcome

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.

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Latest News:

Dr. Kaps spoke at Virginia Tech

Dr. Kaps gave a talk titled "Evaluating Implementations of SHA-3 Candidates" on April 13th as part of the Computer Science Seminar Series at Virgina Tech, National Capital Region. The presentation summarized the implementation results from our and other research groups. Comparing implementations of several functionally equivalent algorithms in a fair and balanced manner is a challenging task. Dr. Kaps briefly highlighted the difficulties and presented tools for fair, comprehensive, and automated evaluation of hardware and software implementations of cryptographic algorithms. (4/13/12)

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Dr. Kaps and Dr. Gaj were awarded SBIR grant with McQ from DARPA

Dr. Kaps and Dr. Gaj have been awarded an SBIR grant with McQ Inc. from DARPA. The project title is Lightweight Public Key Algorithms (PKA) for Lower Power Environments. The project period for Phase 1 is January 1, 2012 to October 31, 2012, and the total amount of the award to GMU is $15,000 for Phase 1 with anticipated total funding of $22,700 including Phase 1 Option. (4/3/12)

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CERG at the Third SHA-3 Candidate Conference

The National Institute of Standards and Technology (NIST) started a public competition to develop a new Secure Hash Algorithm (SHA-3) in November 2007. NIST is expected to announce the winner later in 2012. From the submitted 64 entries only 5 algorithms made it to the final round. On March 22-23, the 3rd and final SHA-3 candidate conference was held in Washington D.C. During this conference research groups from all over the world presented their latest security analysis and implementation results for SHA-3 finalists. The Cryptographic Engineering Research Group (CERG) from GMU contributed to the state of the art of SHA-3 candidate implementations through 4 research papers presented at this conference. The papers covered high speed ASIC, high speed and low resource FPGA, and low resource software implementations. The paper "Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs" was presented by Dr. Gaj and the paper "Lightweight Implementations of SHA-3 Finalists on FPGAs" by Dr. Kaps. The papers "Lessons Learned from Designing a 65nm ASIC for Evaluating Third Round SHA-3 Candidates" and "XBX Benchmarking Results January 2012" were in collaboration with research groups from Switzerland and Germany, respectively and were presented by their researchers. (3/24/12)

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SHARCS 2012 in Washington D.C.

CERG was an organizer of SHARCS 2012 - Special-Purpose Hardware for Attacking Cryptographic Systems workshop held in the Washington Marriott Hotel on March 17-18, 2012. Dr. Kaps served as a general chair of the workshop, and Dr. Gaj was one of the two co-chairs. Graduate students from CERG provided technical and logistic support during the event. This edition of SHARCS had more than 70 participants from 19 countries of 5 continents. The slides of all presentations and the workshop record are posted on the SHARCS 2012 website. An extensive record of the entire series, including all slides and papers from the previous workshops, is available at http://sharcs.org. (3/19/12)

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Dr. Kaps is a member of the Program Committee of (AHSA) Architectures and Hardware for Security Applications 2012

Dr. Kaps is a member of the Program Committee of the special session (AHSA) Architectures and Hardware for Security Applications at the Euromicro Conference on Digital System Design (DSD). DSD addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to micro-architectures, digital circuits and VLSI techniques. DSD 2012 will be held on September 5-8, 2012 in Cesme near Izmir, Turkey. (2/12/12)

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Dr. Gaj is a member of the Program Committee of CHES 2012

Dr. Gaj is a member of the Program Committee of Workshop on Cryptographic Hardware and Embedded Systems CHES 2012. CHES 2012 will be held on September 9-12, 2012 in Leuven, Belgium. (1/15/12)

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Seminars:

Homomorphic Cryptography Survey

David Arrlen, MS CpE Scholarly Paper
Date: Monday, April 30th, 5:00 PM, Location: Engineering Building, Room 3507

Abstract

Homomorphic cryptography provides a means of performing mathematic operations in both the ciphertext and plaintext domains with correct results in each. Mobile devices have many limitations due to their low power design requirements that make offloading computations to the cloud desirable. The cloud is an untrusted computing resource and therefore should not have access to sensitive data. Using a homomorphic cryptosystem, the mobile device can send sensitive operands in encrypted form to the cloud for computation and decrypt the result received from the cloud. This paper discusses previous work from Rivest's first publication on the subject to Gentry's fully homomorphic cryptosystem as well as applications thereof.

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PCI Express Interface for High Performance FPGA Boards

Patrick Daderko, MS CpE Scholarly Paper
Date: Monday, April 30th, 3:30 PM, Location: Engineering Building, Room 3507

Abstract

PCI Express (PCIe) has become a common standard in computing, providing a versatile high-speed communication bus. Many high performance FPGA boards utilize PCIe for communication, which provide opportunities and challenges for engineers. Specific development and application boards using Xilinx Virtex 6 and Altera Stratix IV FPGAs will be compared, reviewing connectivity, on-board hardware resources, and other details.

There will also be discussion of PCIe FPGA IP cores, drivers, and API software. Specifically, Jungo WinDriver, a cross-platform and cross-device driver development software, will be described, analyzed, and compared to other offerings available. IP cores from Xilinx and Altera, as well as Northwest Logic and PLDA will also be described and compared.

Included in all topics will be discussion of performance, resources, price, development time and effort, and related details.

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Market Survey of Low Powered FPGA Devices

Aditya Mehta, MS CpE Scholarly Paper
Date: Monday, April 30th, 1:00 PM, Location: Engineering Building, Room 3507

Abstract

Field Programmable Gate Arrays (FPGAs) have been gaining popularity due to their much lower non-recurring cost and their attractive cost/performance ratio in electronic products. Furthermore, the recent advent of low-power FPGAs for battery powered devices has spurred this trend. Hence they are being employed on a large scale in many designs. Designers have traditionally relied on application-specific integrated circuits (ASICs), not FPGAs, to meet their low-power constraints. With longer time-to-market, rising non-recurring engineering charges (NREs), and a lack of flexibility to address changing standards and late-stage design modifications, hardwired ASICs are riskier and often impractical for applications with short product life cycles.

This presentation surveys the many low powered FPGAs that are available in the market currently. The vendors surveyed are Xilinx, Microsemi, Lattice Semiconductor, Altera and SiliconBlue Technologies (a Lattice Semiconductor Company). An analysis of the technologies that are used to make sure these FPGAs consume as little power as possible is made, and a comparison of the different low power features available on these FPGAs. Each FPGA vendor offer different intellectual property (IP) cores for their FPGAs like processor IP cores, interface/bus/bridge IP, peripheral IP or Communications IP. This presentation will discuss some of the different IP cores offered by the vendors.

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Distributed Computing and Optimization Space Exploration for Fair and Efficient Benchmarking of Cryptographic Cores in FPGAs

Benjamin Brewster, MS CpE Master's Thesis Defense
Date: Monday, April 30th, 10:00 AM, Location: Engineering Building, Room 3507

Abstract

Benchmarking of digital designs targeting FPGAs is a time intensive and challenging process. Benchmarking results depend on a myriad of variables beyond the properties inherent to the designs being evaluated, encompassing the tools, tool options, FPGA families, and languages used. In this thesis we will be discussing enhancements made to the ATHENa benchmarking tool to utilize distributed computing as well as optimization space exploration techniques to increase the efficiency of the ATHENa benchmarking process. Capabilities of the environment are demonstrated using four example designs from the SHA-3 cryptographic hashing function competition, BLAKE, JH, Keccak and Skein.

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SHA-3 Finalist Keccak on FPGAs

Smriti Gurung, MS CpE Master's Thesis Defense
Date: Friday, April 27th, 11:00 AM, Location: Engineering Building, Room 3202

Abstract

The Secure Hash Algorithm (SHA) is a cryptographic hash function published by the National Institute of Standard and Technology (NIST) as a U.S Federal Information and Processing Standard (FIPS). In the past few years, a flaw discovered in the SHA-1 shows its vulnerability to attacks. The current hashing standard SHA-2 which shares similarities to SHA-1 is therefore under scrutiny for a possible attack. In 2007, NIST announced the SHA-3 competition in hopes of finding a new algorithm with higher margin of security and which is also more efficient in terms of software and hardware performance. Out of the 51 candidates selected in round one, only five remain in the third and final round namely BLAKE, Grostl, JH, Keccak and Skein.

So far, several high speed implementations of the SHA-3 algorithms on FPGAs have been published. However, these implementations become impractical for resource constrained environments where area is a limitation for e.g small battery powered hand held devices. Our goal was to design different lightweight architectures for the sponge construction based algorithm Keccak. We tried to evaluate its performance with respect to its scalability. In this study all the implementations were designed with an area constraint of 800 slices or 400-600 slices and one block RAM, targeting the low cost Spartan-3 devices. Designs were also synthesized on different Xilinx and Altera devices for comparison with other published results. Although our implementation of Keccak is one of the smallest reported so far, this reduction came at the cost of lower throughput to area ratio.

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Latest Publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

• C. Wenzel-Benner, J. Gräf, J. Pham, and J.-P. Kaps, XBX benchmarking results january 2012, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
• J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
• K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
• F.K. Gürkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
• R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
• J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [Bibtex]
• A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'11, IEEE, pages 242–248, Dec, 2011 [Bibtex]
• E. Homsirikamol, M. Rogawski, and K. Gaj, Throughput vs. Area trade-offs architectures of five Round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs, Workshop on Cryptographic Hardware and Embedded Systems CHES 2011, LNCS, volume 6917, Springer Berlin / Heidelberg, pages 491–506, Sep, 2011 [Bibtex]
• R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [Bibtex]
• X. Xin, J.-P. Kaps, and K. Gaj, A configurable ring-oscillator-based PUF for Xilinx FPGAs, 14th EUROMICRO Conference on Digital System Design – DSD'11, IEEE, pages 651–657, Aug, 2011 [pre-print, pdf] [Bibtex] Nominated for Best Paper Award
• E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]