CERG Support of CAESAR

SHARCS 2012

CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Members of CERG have developed the CAESAR Hardware API for authenticated ciphers, approved by the CAESAR Committee. Our group has also developed comprehensive Development Package, including VHDL and Python code common for all candidates, and the corresponding Implementer's Guide. CERG has contributed optimized high-speed RTL implementations for 19 Round 2 CAESAR Candidates and AES-GCM. Members of our team have also conducted comprehensive FPGA benchmarking of all Round 2 implementations, submitted by 14 hardware design teams from all over the world. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. The summary of the Round 2 RTL benchmarking effort and an alternative benchmarking methodology based on High-Level Synthesis were presented at DIAC 2016. Additionally, two current members (Ice and Dr. Gaj) and one former member of CERG (Marcin) were co-authors of ICEPOLE, a high-speed, hardware-oriented Round 2 CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) could be used to provide high data processing rates.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Latest News:

Dr. Gaj will give a keynote address at CADICS 2016

Dr. Gaj will give a keynote address at the CADICS - Computer-Aided Design and Implementation for Cryptography and Security - workshop, co-located with the 2016 International Conference on Computer Aided Design - ICCAD, to be held in Austin, TX, on Nov. 7-10, 2016. Dr. Gaj's keynote, co-authored with Ekawat Homsirikamol, Farnoud Farahmand, Ahmed Ferozpuri, Marcin Rogawski, and Panasayya Yalla, is entitled "Computer-Aided Design Tools and Methodologies for Evaluating Candidates in Cryptographic Contests," and will be held on Nov. 10. (2016/10/23)


Dr. Kaps attended SPEED-B

Dr. Kaps attended the SPEED-B - Software performance enhancement for encryption and decryption, and benchmarking conference held in Utrecht, The Netherlands, on October 19-21, 2016. As part of this conference he gave an invited talk on the eXtended eXternal Benchmarking eXtension (XXBX) a tool to benchmark performance of cryptographic algorithms on microcontrollers. More information on XXBX can be found on our XXBX Page. (10/25/16)


Members of CERG attended NIST Lightweight Cryptography Workshop

Dr. Kaps, William Diehl, Ahmed Ferozpuri, and Panasayya Yalla attended NIST Lightweight Cryptography Workshop 2016, held in Gaithersburg, MD, on Oct. 17-18, 2016. All papers and slides presented at the workshop can be found here. (2016/10/19)


Dr. Gaj and Dr. Kaps attended DIAC 2016

Dr. Gaj and Dr. Kaps attended DIAC 2016, the Directions in Authenticated Ciphers workshop, held in Nagoya, Japan, on September 26-27, 2016. As a part of this workshop, Dr. Gaj gave a talk entitled "Toward Fair and Comprehensive Benchmarking of CAESAR Candidates in Hardware: Standard API, High-Speed Implementations in VHDL/Verilog, and Benchmarking Using FPGAs," co-authored with Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Michael X. Lyons, and Panasayya Yalla, as well as the presentation entitled "An Alternative Approach to Hardware Benchmarking of CAESAR Candidates Based on the Use of High-Level Synthesis Tools," co-authored with Ekawat Homsirikamol. Dr. Kaps gave a talk entitled "Enhancing CAESAR Hardware API Support for Lightweight Architectures," co-authored with Panasayya Yalla. (09/28/2016)


Dr. Gaj is a member of the Program Committee of DATE 2017

Dr. Gaj is a member of the Program Committee of DATE 2017: Design, Automation and Test in Europe conference, in Track A: Application Design, Topic A5: Secure Systems. Multiple student members of CERG are contributing their time and expertise serving as sub-reviewers for the aforementioned conference. (09/20/2016)


Ekawat Homsirikamol gave a PhD Seminar

Ekawat Homsirikamol gave the PhD seminar entitled "From C to Hardware: Toward Using High-Level Synthesis for Hardware Benchmarking of Candidates in Cryptographic Contests," on September 9, 2016. His PhD defense is tentatively scheduled for November 18, 2016. (09/10/2016)


William Diehl attended DSD 2016

William Diehl attended the 19th Euromicro Conference on Digital System Design, DSD 2016, held in Limassol, Cyprus, August 31-September 2, 2016. As part of the conference, William presented the paper "RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two" and gave a poster presentation "Implementation of a Boolean Masking Scheme for the SCREAM Cipher." (09/03/2016)


Dr. Gaj attended FPL 2016

Dr. Gaj attended the 26th International Conference on Field-Programmable Logic and Applications, FPL 2016, held in Lausanne, Switzerland, August 29-September 2, 2016. As part of this conference, Dr. Gaj gave a short talk and presented a poster, entitled "Hardware-Software Codesign of RSA for Optimal Performance vs. Flexibility Trade-off," based on the paper co-authored with Malik Umar Sharif, Rabia Shahid, and Marcin Rogawski. Additionally, Dr. Gaj attended the workshop FPGAs for Software Programmers, FSP 2016, and the tutorial Pynq for Zynq Devices, both co-located with FPL. (09/03/2016)


Presentation summarizing benchmarking of Round 2 CAESAR Candidates

The GMU Benchmarking Team has published and announced a comprehensive presentation, entitled "Benchmarking of Round 2 CAESAR Candidates in Hardware: Methodology, Designs & Results," made available at the CAESAR page of the ATHENa website. The GMU Team has contributed high-speed RTL implementations of AES-GCM and 19 CAESAR Candidates, including a total of 25 variant-architecture pairs, with multiple extensions and improvements published in the period from June 30 to August 11, 2016. (08/11/2016)


Bilal Habib defended his PhD Thesis

Bilal Habib defended his PhD Thesis, entitled "Design, Implementation and Analysis of Efficient FPGA based Physical Unclonable Functions," on July 26, 2016. The members of his dissertation committee included Dr. Gaj (co-Chair), Dr. Kaps (co-Chair), Dr. Homayoun, and Dr. Rangwala. In August, Bilal started his new assignment as a Postdoctoral Fellow at the Northern Arizona University in Flagstaff, Arizona, as a part of the research group of Prof. Bertrand Cambou. (08/10/2016)


Benchmarking of Round 2 CAESAR Candidates

The CERG Team announced the results of hardware benchmarking of Round 2 CAESAR Candidates on July 25, 2016. The benchmarking effort involved over 40 distinct submission packages covering 28 candidate families, submitted by 13 groups from all over the world. About 20 implementations have been developed by members of CERG. All implementations have been benchmarked using four high-performance FPGA families: Virtex 6, Virtex 7, Stratix IV, and Stratix V. Additionally, implementations of 10 lightweight algorithms have been benchmarked using four low-cost FPGA families: Spartan 6, Artix 7, Cyclone IV, and Cyclone V. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. Additionally, two web-based tables, describing, respectively all submission packages and all variant-architecture pairs, are available at the ATHENa Website. Majority of the designs submitted for benchmarking are compliant with the CAESAR Hardware API, developed by members of CERG, and approved by the CAESAR Committee. (07/25/2016)


Dr. Gaj and Dr. Kaps attended CryptArchi 2016

Dr. Gaj and Dr. Kaps attended CryptArchi 2016, held in La Grande Motte near Montpellier, France, on June 21-24, 2016. Dr. Gaj gave a talk entitled "Fair and Comprehensive Benchmarking of 29 Round 2 CAESAR Candidates in Hardware: Preliminary Results," and Dr. Kaps delivered a presentation entitled "A Scalable ECC Processor Implementation for High-Speed and Lightweight". (06/25/2016)


Panasayya Yalla and Dr. Kaps gave hardware demo at HOST 2016

Panasayya Yalla and Dr. Kaps attended the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, held in McLean, VA, on May 3-5, 2016. As a part of the symposium, they gave a hardware demo of the CERG Flexible, Opensource workbench for Side-channel analysis (FOBOS), designed by Rajesh Velegalati, Panasayya Yalla, and Dr. Kaps. (05/06/2016)


Dr. Viktor Fischer visited GMU

Dr. Viktor Fischer, a Professor at Jean Monnet University, Saint-Etienne, France, visited GMU on May 4, 2016, and gave the ECE Departmental seminar entitled "Sources of Randomness in Digital Devices and Their Testability". Dr. Fischer is a founder of the CryptArchi workshop series on cryptographic architectures embedded in logic devices, attended by CERG faculty and students regularly every year since the first edition of the workshop in January 2003. He is also a world-renowned expert in the area of true random number generation. His talk was followed by meetings with several GMU faculty members and CERG graduate students. (05/05/2016)


William Diehl gave a poster presentation at FCCM 2016

William Diehl attended the 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, held in Washington DC, on May 1-3, 2016. As a part of the symposium, William gave the poster presentation, entitled "High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two." (05/04/2016)


Ludovic Lescieux from ALPhANOV visited CERG

On April 29, 2016, CERG hosted Mr. Ludovic Lescieux from ALPhANOV - an optics and lasers technology center based in Talence, near Bordeaux in France. As a part of his visit, Mr. Lescieux gave the presentation and demo about the ALPhANOV equipment that can be used for fault attacks against integrated circuits. In particular, the presentation covered the Pulse-on-Demand Modules (PDM) and Multispot Laser Platform Control. (04/30/2016)


Dr. Bertrand Cambou visited GMU

Dr. Bertrand Cambou, from Northern Arizona University visited CERG on April 4, 2016, and gave the ECE Departmental seminar entitled "PUF designed with Resistive RAM and Ternary States". His talk was followed by individual meetings with several Computer Engineering faculty and CERG graduate students. (04/05/2016)


Bilal Habib attended ARC 2016

Bilal Habib attended the 12th International Symposium on Reconfigurable Computing, ARC 2016, held in Mangaratiba, Rio de Janeiro, Brazil, on 22-24 March, 2016. During this conference Bilal gave a talk entitled: "A Comprehensive Set of Schemes for PUF Response Generation". The scripts described in this presentation and sample raw data have been made available at the CERG PUF page. (03/25/2016)


Ahmed Ferozpuri and Dr. Gaj attended PQCrypto 2016

Ahmed Ferozpuri and Dr. Gaj attended the 7th International Conference on Post-Quantum Cryptography, PQCrypto 2016, preceded by the Post-Quantum Cryptography Winter School, held in Fukuoka, Japan, on February 22-26, 2016. During this conference, NIST announced its upcoming Call for Proposals regarding quantum-resistant cryptographic algorithms for new public-key cryptographic standards, to be published in Fall 2016. PQCrypto 2016 included the Hot Topic Session, during which Ahmed Ferozpuri gave a 5-minute presentation entitled "A Framework for Evaluating Software/Hardware Implementations of Post-Quantum Public-Key Algorithms Using Zynq SoC". (02/27/2016)


Seminars:

Sources of Randomness in Digital Devices and Their Testability

Dr. Viktor Fischer, Hubert Curien Laboratory, Jean Monnet University, Saint-Etienne, France
Date: Wednesday, May 4th, 10:30 AM - 11:30 AM
Location: Engineering Building, Room 4801

Digital electronic devices are often used to implement data security systems-on-chip (SoC), like smart cards. Random bit stream generators constitute one of the main building blocks of such systems. They use some uncontrollable physical analog phenomenon as a source of randomness. The random variations in this analog process must be converted to a digital bitstream using some intrinsic analog to digital conversion or some extrinsic digitization technique. This conversion should be feasible using purely digital technology, because the use of some analog electronic blocks inside the device would increase the total cost of the system. (Full Announcement)


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]
  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, Efficient SR-latch PUF, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 205–216, Apr., 2015 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 217-228, Apr, 2015 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]