SHARCS 2012 in Washington D.C.

SHARCS 2012

CERG was an organizer of SHARCS 2012 - Special-Purpose Hardware for Attacking Cryptographic Systems workshop held in the Washington Marriott Hotel on March 17-18, 2012. Dr. Kaps served as a general chair of the workshop, and Dr. Gaj was one of the two co-chairs. Graduate students from CERG provided technical and logistic support during the event. This edition of SHARCS had more than 70 participants from 19 countries of 5 continents. The slides of all presentations and the workshop record are posted on the SHARCS 2012 website. An extensive record of the entire series, including all slides and papers from the previous workshops, is available at http://sharcs.org. (3/19/12)

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.

Latest News:

Dr. Gaj awarded a patent for Montgomery Multiplication Architecture

Dr. Gaj and Dr. Huang (University of Arkansas) have been awarded the U.S. patent no. 8,386,546 B2, entitled "Montgomery Multiplication Architecture," issued on February 26, 2013. The patent is based on the paper "New Hardware Architectures for Montgomery Modular Multiplication Algorithm," (preprint) published in the IEEE Transactions on Computers in July 2011. The patent will remain valid for 20 years, plus a patent term adjustment of 495 days, from the day of initial filing (March 1, 2010). (04/13/13)

Dr. Gaj is a member of the Program Committees of LightSec 2013, ReCoSoc 2013, CHES 2013, DSD 2013, SPACE 2013, and Asiacrypt 2013

Dr. Gaj is a member of the Program Committees for the following conferences:

  • LightSec 2013: Second International Workshop on Lightweight Cryptography for Security & Privacy, to be held in Gebze, Turkey, on May 6-7, 2013
  • ReCoSoC 2013: 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, to be held in Darmstadt, Germany, on July 10-12, 2013
  • CHES 2013: Workshop on Cryptographic Hardware and Embedded Systems, to be held in Santa Barbara, USA, on August 20-23, 2013
  • DSD 2013: 16th Euromicro Conference on Digital System Design, to be held in Santander, Spain, on September 4-6, 2013
  • SPACE 2013: 3rd International Conference on Security, Privacy, and Applied Cryptography Engineering, to be held in Kharagpur, India, on October 19-23, 2013, and
  • Asiacrypt 2013: 19th Annual International Conference on the Theory and Application of Cryptology and Information Security, to be held in Bangalore, India, on December 1-5, 2013.

(03/03/13)

Microsemi SmartFusion2 SoC FPGAs SpeedWay Design Workshop

CERG students, Malik Umar Sharif and Panasayya Yalla attended the Microsemi SmartFusion2 SoC FPGAs SpeedWay Design Workshop, held in Baltimore on February 20, 2013. (02/20/13)

Phase I Option Navy Project with McQ Inc.

CERG Team is collaborating with McQ Inc. on the Phase I Option SBIR Project entitled "Distributed Storage in Wireless Mesh Networks", sponsored by USMC. The period of performance is February 19-May 31, 2013. (02/19/13)

Keccak Team at NIST

The GMU CERG Team has attended the presentation entitled " Keccak and the SHA-3 Standardization" given by the Keccak Team at NIST in Gaithersburg, MD, on February 6, 2013. (02/06/13)

Rajesh Velegalati's Internship at Riscure

Rajesh Velegalati is conducting an internship at Riscure North America in San Francisco, CA. His work focuses on Electro Magnetic and Fault Attacks on Smart Phones. The period of the internship is from January 28 to August 16, 2013. (01/28/13).

Ekawat Homsirikamol's Internship at Acadia Optronics LLC

Ekawat Homsirikamol ("Ice") is conducting an internship at Acadia Optronics LLC in Rockville, MD. His work focuses on the Acadia's 100 Gb/s FPGA-based platforms used to enhance end-to-end data transmission security. The initial period of the internship is from January 28 to May 15, 2013. (01/28/13)

Dr. Kaps is a member of the Program Committee of (AHSA) Architectures and Hardware for Security Applications 2013

Dr. Kaps is a member of the Program Committee of the special session (AHSA) Architectures and Hardware for Security Applications at the Euromicro Conference on Digital System Design (DSD). DSD addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to micro-architectures, digital circuits and VLSI techniques. DSD 2013 will be held on September 4-6, 2013 in Santander, Spain. (01/21/13)

Seminars:

Crypto Evening

ECE 746 Advanced Cryptography, Project Presentations
Date: Tuesday, May 7th, 4:30 PM - 8:00 PM, Location: TBD

Join us for an evening of exciting presentations by ECE 746 students. The exact schedule will be posted here shortly. Simrit Kaur Arora, Robert Lorentz, Yamini Ravishankar, and Aaron Hunter of our research group will be presenting. Please come over to cheer them on!

Latest Publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • R. Velegalati and J.-P. Kaps, Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis, May, 2012, Work in Progress (WiP), Third International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2012 [Bibtex]
  • C. Wenzel-Benner, J. Gräf, J. Pham, and J.-P. Kaps, XBX benchmarking results January 2012, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
  • F.K. Gürkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
  • R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [Bibtex]
  • A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'11, IEEE, pages 242–248, Dec, 2011 [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Throughput vs. Area trade-offs architectures of five Round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs, Workshop on Cryptographic Hardware and Embedded Systems CHES 2011, LNCS, volume 6917, Springer Berlin / Heidelberg, pages 491–506, Sep, 2011 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [Bibtex]
  • X. Xin, J.-P. Kaps, and K. Gaj, A configurable ring-oscillator-based PUF for Xilinx FPGAs, 14th EUROMICRO Conference on Digital System Design – DSD'11, IEEE, pages 651–657, Aug, 2011 [pre-print, pdf] [Bibtex] Nominated for Best Paper Award
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]