CERG Support of CAESAR


CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Members of CERG have developed the CAESAR Hardware API for authenticated ciphers, approved by the CAESAR Committee. Our group has also developed comprehensive Development Package, including VHDL and Python code common for all candidates, and the corresponding Implementer's Guide. CERG has contributed optimized high-speed RTL implementations for 24 Round 2 CAESAR Candidates and AES-GCM. Members of our team have also conducted comprehensive FPGA benchmarking of all Round 2 implementations, submitted by 14 hardware design teams from all over the world. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. The summary of the Round 2 RTL benchmarking effort and an alternative benchmarking methodology based on High-Level Synthesis were presented at DIAC 2016. Additionally, two current members (Ice and Dr. Gaj) and one former member of CERG (Marcin) were co-authors of ICEPOLE, a high-speed, hardware-oriented Round 2 CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) could be used to provide high data processing rates.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


A Generic High-Speed Hardware Implementation of NTRUEncrypt SVES

Malik Umar Sharif, ECE PhD Seminar
Date: Monday, July 24th, 11:00 AM - 12:00 PM
Location: Engineering Building, Room 3507

NTRUEncrypt is a polynomial ring-based public-key encryption scheme that was first introduced at Crypto'96. In 2008, an extended version of this algorithm was published as the IEEE 1363.1 Standard Specification for Public Key Cryptographic Techniques Based on Hard Problems over Lattices. Within the standard, the described algorithm is called Short Vector Encryption Scheme - SVES. The recent renewed interest in NTRU is at least partially driven by its presumed resistance to any efficient attacks using quantum computers. In Feb. 2016, NIST has announced its plans of starting the standardization effort in the area of post-quantum cryptography. This effort is likely to last years and result in an entire portfolio of algorithms capable of replacing current public-key cryptography schemes. As a part of this standardization process, fair and efficient benchmarking of PQC algorithms in hardware and software becomes a necessity.

We present a high-speed hardware implementation of NTRUEncrypt Short Vector Encryption Scheme (SVES), fully compliant with the aforementioned IEEE standard. Our design supports two representative parameter sets, ees1087ep1 and ees1499ep1, optimized for speed, which provide security levels of 192 and 256 bits, respectively. Our implementation follows an earlier proposed Post-Quantum Cryptography (PQC) Hardware Application Programming Interface (API). As a first design following this API, it provides a reference that can be adopted in any future implementations of post-quantum cryptosystems. We present the detailed flow and block diagrams, as well as results in terms of latency (in clock cycles), maximum clock frequency, and resource utilization. We also report the speedup of our implementation in Xilinx Field Programmable Gate Arrays (FPGAs) as compared to existing software implementations of NTRUEncrypt SVES, with equivalent functionality. Our results show a significant speed-up of hardware vs. software, and very different percentage contributions of the execution times for equivalent operations executed in these two different environments. Our project is intended to pave the way for the future comprehensive, fair, and efficient hardware benchmarking of the most promising encryption, signature, and key agreement schemes from each of several major post-quantum public-key cryptosystem families.

A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems

Rabia Shahid, ECE PhD Seminar
Date: Monday, July 24th, 10:00 AM - 11:00 AM
Location: Engineering Building, Room 3507

Cryptographic engineering is a field that combines cryptology, algebraic geometry, and number theory with methods from computer arithmetic, digital system design, and computer architecture. Unfortunately, most of the researchers working in this area are either mathematicians/cryptographers or computer engineers, specializing in their respective fields. The theoretical complexities related to number theory and abstract algebra in the majority of public-key cryptosystems can easily prevent computer engineers from fully optimizing their designs. In this talk, we describe a possible bridge between these two domains, demonstrated using a family of Elliptic Curve Cryptosystems (ECC). We present the design of a configurable and generic execution unit for ECC that serves as a coprocessor to perform operations involved during a scalar multiplication. The execution unit is supported by a software static scheduler to automate the cumbersome process of manual scheduling of operations involved in ECC. The arithmetic unit performs the operations at the lowest level of hierarchy, i.e., prime field arithmetic. We focus on optimizing the overall performance of the cryptoprocessor by using an optimal number of multiplier units, capable of taking full advantage of the parallelism present in the algorithm and a single modular adder/subtractor, working in parallel with multipliers. An instruction set architecture capable of supporting all required instructions is designed, along with the coprocessor that can process multiple batches of instructions using the arithmetic unit. We report results for an entire scalar multiplication in terms of latency in clock cycles and in absolute time units. We also demonstrate that the entire setup is generalizable to any cryptosystem that involves modular multiplications and modular additions/subtractions at the lowest level of hierarchy.

Latest News:

Dr. Gaj and Dr. Kaps attended PQCrypto 2017

Dr. Gaj and Dr. Kaps attended the 8th International Conference on Post-Quantum Cryptography, PQCrypto 2017, held in Utrecht, the Netherlands, June 26-28, 2017. During the Recent Result Session on June 26, chaired by Dr. Wouter Castryck, Dr. Gaj delivered a short presentation entitled "High-Speed Hardware for NTRUEncrypt-SVES: Lessons Learned", co-authored with Malik Umar Sharif. Additionally, Dr. Kaps attended a week-long Summer School on Post-Quantum Cryptography (organized by the H2020 project PQCRYPTO), and Dr. Gaj attended a two-day Executive School on Post-Quantum Cryptography (organized by the H2020 project ECRYPT-CSA). Both schools were held at the Technische Universiteit Eindhoven on June 19-23 and June 22-23, 2017, respectively. (06/29/2017)

Dr. Gaj spoke at CryptArchi 2017

Dr. Gaj spoke at the 15th International Workshop on Cryptographic Architectures Embedded in Logic Devices, CryptArchi 2017, held in Smolenice, Slovakia, on June 18-21, 2017. He delivered a talk entitled "Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems," co-authored with Malik Umar Sharif and Ahmed Ferozpuri. (06/22/2017)

Dr. Gaj spoke at the Workshop on Hardware Benchmarking 2017

Dr. Gaj spoke at the Workshop on Hardware Benchmarking, held in Bochum, Germany, on June 7, 2017. He delivered an invited talk entitled "Fair and Efficient Hardware Benchmarking of Candidates in Cryptographic Contests". (06/07/2017)

Rabia Shahid spoke at RAW 2017

Rabia Shahid spoke at the 24th Reconfigurable Architecture Workshop - RAW 2017, co-located with the 31st Annual IEEE International Parallel and Distributed Processing Symposium - IEEE IPDPS 2017, held in Orlando, Florida, on May 29-June 2, 2017. She delivered a talk entitled "A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems," based on the paper co-authored with Ted Winograd and Dr. Gaj. (06/01/2017)

Farnoud Farahmand earned internship at Google

Farnoud Farahmand has earned the position of the Hardware Engineer Intern at Google in Mountain View, CA, to be held between May 30 and August 25, 2017. (05/30/2017)

Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards

CERG Members, Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards, handed to them by the ECE Department Chair, Prof. Monson Hayes, during the ECE Convocation Reception on May 18, 2017. Here is a photo of all awardees together with their academic advisor Dr. Gaj. (05/19/2017)

William Diehl qualified to the finals of the 3M Thesis Competition

William Diehl qualified to the finals of the 3-Minute Thesis competition. The preliminary round was held on March 3, 2017, in the HUB Rooms 4 & 5. 48 GMU doctoral students entered the contest, of whom 20 were from the Volgenau School of Engineering. Each contestant had three minutes (and one Powerpoint slide) to explain his/her research to a general audience. William was the only student representing CERG. The finals were held on Saturday, March 25, at Mason's Arlington Campus. They were part of the Mason Graduate Interdisciplinary Conference. An article about the competition, with a quote from William, was written by Martha Bushong, and published in News at Mason. (03/06/2017)

Dr. Gaj's research featured in the Spring 2017 ECE Newsletter

Dr. Gaj's research has been featured in the Spring 2017 ECE Newsletter. The article about Dr. Gaj is called "Battles for Cryptographic Algorithms". (02/11/2017).

Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]