CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Two current (Ice and Dr. Gaj) and one former member of CERG (Marcin) are co-authors of ICEPOLE, a high-speed, hardware-oriented CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) can be used to provide high data processing rates. The paper about ICEPOLE has been presented at CHES 2014 in September 2014. In July 2015, ICEPOLE advanced to the second round of the CAESAR competition, and in September 2015, its tweaked version was presented at DIAC 2015 in Singapore. Independently, members of CERG developed a new hardware API for authenticated ciphers, which can be used in any future hardware implementations of all CAESAR candidates, presented for the first time at CryptArchi 2015. The specification of the GMU API is accompanied by a substantial number of supporting materials (a universal testbench, a script to generate test vectors, the PreProcessor and PostProcessor source codes, VHDL wrappers, etc.), simplifying the development and benchmarking of high-speed implementations of CAESAR candidates. Additionally, CERG supports an interactive, on-line database of FPGA results for CAESAR candidates and current authenticated encryption standards. Multiple high-speed and low-area implementations of CAESAR candidates are currently developed and benchmarked by members of CERG using both traditional and novel design methodologies. (8/17/15)

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Sources of Randomness in Digital Devices and Their Testability

Dr. Viktor Fischer, Hubert Curien Laboratory, Jean Monnet University, Saint-Etienne, France
Date: Wednesday, May 4th, 10:30 AM - 11:30 AM
Location: Engineering Building, Room 4801

Digital electronic devices are often used to implement data security systems-on-chip (SoC), like smart cards. Random bit stream generators constitute one of the main building blocks of such systems. They use some uncontrollable physical analog phenomenon as a source of randomness. The random variations in this analog process must be converted to a digital bitstream using some intrinsic analog to digital conversion or some extrinsic digitization technique. This conversion should be feasible using purely digital technology, because the use of some analog electronic blocks inside the device would increase the total cost of the system. (Full Announcement)

Latest News:

Benchmarking of Round 2 CAESAR Candidates

The CERG Team announced the results of hardware benchmarking of Round 2 CAESAR Candidates on July 25, 2016. The benchmarking effort involved over 40 distinct submission packages covering 28 candidate families, submitted by 13 groups from all over the world. About 20 implementations have been developed by members of CERG. All implementations have been benchmarked using four high-performance FPGA families: Virtex 6, Virtex 7, Stratix IV, and Stratix V. Additionally, implementations of 10 lightweight algorithms have been benchmarked using four low-cost FPGA families: Spartan 6, Artix 7, Cyclone IV, and Cyclone V. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. Additionally, two web-based tables, describing, respectively all submission packages and all variant-architecture pairs, are available at the ATHENa Website. Majority of the designs submitted for benchmarking are compliant with the CAESAR Hardware API, developed by members of CERG, and approved by the CAESAR Committee. (07/25/2016)

Dr. Gaj and Dr. Kaps attended CryptArchi 2016

Dr. Gaj and Dr. Kaps attended CryptArchi 2016, held in La Grande Motte near Montpellier, France, on June 21-24, 2016. Dr. Gaj gave a talk entitled "Fair and Comprehensive Benchmarking of 29 Round 2 CAESAR Candidates in Hardware: Preliminary Results," and Dr. Kaps delivered a presentation entitled "A Scalable ECC Processor Implementation for High-Speed and Lightweight". (06/25/2016)

Panasayya Yalla and Dr. Kaps gave hardware demo at HOST 2016

Panasayya Yalla and Dr. Kaps attended the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, held in McLean, VA, on May 3-5, 2016. As a part of the symposium, they gave a hardware demo of the CERG Flexible, Opensource workbench for Side-channel analysis (FOBOS), designed by Rajesh Velegalati, Panasayya Yalla, and Dr. Kaps. (05/06/2016)

Dr. Viktor Fischer visited GMU

Dr. Viktor Fischer, a Professor at Jean Monnet University, Saint-Etienne, France, visited GMU on May 4, 2016, and gave the ECE Departmental seminar entitled "Sources of Randomness in Digital Devices and Their Testability". Dr. Fischer is a founder of the CryptArchi workshop series on cryptographic architectures embedded in logic devices, attended by CERG faculty and students regularly every year since the first edition of the workshop in January 2003. He is also a world-renowned expert in the area of true random number generation. His talk was followed by meetings with several GMU faculty members and CERG graduate students. (05/05/2016)

William Diehl gave a poster presentation at FCCM 2016

William Diehl attended the 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, held in Washington DC, on May 1-3, 2016. As a part of the symposium, William gave the poster presentation, entitled "High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two." (05/04/2016)

Ludovic Lescieux from ALPhANOV visited CERG

On April 29, 2016, CERG hosted Mr. Ludovic Lescieux from ALPhANOV - an optics and lasers technology center based in Talence, near Bordeaux in France. As a part of his visit, Mr. Lescieux gave the presentation and demo about the ALPhANOV equipment that can be used for fault attacks against integrated circuits. In particular, the presentation covered the Pulse-on-Demand Modules (PDM) and Multispot Laser Platform Control. (04/30/2016)

Dr. Bertrand Cambou visited GMU

Dr. Bertrand Cambou, from Northern Arizona University visited CERG on April 4, 2016, and gave the ECE Departmental seminar entitled "PUF designed with Resistive RAM and Ternary States". His talk was followed by individual meetings with several Computer Engineering faculty and CERG graduate students. (04/05/2016)

Bilal Habib attended ARC 2016

Bilal Habib attended the 12th International Symposium on Reconfigurable Computing, ARC 2016, held in Mangaratiba, Rio de Janeiro, Brazil, on 22-24 March, 2016. During this conference Bilal gave a talk entitled: "A Comprehensive Set of Schemes for PUF Response Generation". The scripts described in this presentation and sample raw data have been made available at the CERG PUF page. (03/25/2016)

Ahmed Ferozpuri and Dr. Gaj attended PQCrypto 2016

Ahmed Ferozpuri and Dr. Gaj attended the 7th International Conference on Post-Quantum Cryptography, PQCrypto 2016, preceded by the Post-Quantum Cryptography Winter School, held in Fukuoka, Japan, on February 22-26, 2016. During this conference, NIST announced its upcoming Call for Proposals regarding quantum-resistant cryptographic algorithms for new public-key cryptographic standards, to be published in Fall 2016. PQCrypto 2016 included the Hot Topic Session, during which Ahmed Ferozpuri gave a 5-minute presentation entitled "A Framework for Evaluating Software/Hardware Implementations of Post-Quantum Public-Key Algorithms Using Zynq SoC". (02/27/2016)

Latest Publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]
  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, Efficient SR-latch PUF, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 205–216, Apr., 2015 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 217-228, Apr, 2015 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]