ICEPOLE and CERG Support of CAESAR

SHARCS 2012

CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Two current (Ice and Dr. Gaj) and one former member of CERG (Marcin) are co-authors of ICEPOLE, a high-speed, hardware-oriented CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) can be used to provide high data processing rates. The paper about ICEPOLE has been presented at CHES 2014 in September 2014, and in July 2015, ICEPOLE advanced to the second round of the CAESAR competition. Independently, members of CERG developed a new hardware API for authenticated ciphers, which can be used in any future hardware implementations of all CAESAR candidates, presented for the first time at CryptArchi 2015. The specification of the GMU API is accompanied by a substantial number of supporting materials (a universal testbench, a script to generate test vectors, the PreProcessor and PostProcessor source codes, VHDL wrappers, etc.), simplifying the development and benchmarking of high-speed implementations of CAESAR candidates. Additionally, CERG supports an interactive, on-line database of FPGA results for CAESAR candidates and current authenticated encryption standards. Multiple high-speed and low-area implementations of CAESAR candidates are currently developed and benchmarked by members of CERG using both traditional and novel design methodologies. (8/17/15)

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Seminars:

Exploiting Cache-based Side Channels in Public Clouds

Thomas Eisenbarth, Assistant Professor, Worcester Polytechnic Institute, Worcester, MA
Date: Tuesday, August 11th, 3:00 PM - 4:00 PM
Location: Engineering Building, Room 3507

Cloud computing services are more popular than ever with their ease of access, low cost and real-time scalability. Security of the cloud computing infrastructure relies on logical isolation between virtual machines through sandboxing. However, isolation is not perfect, and side channels caused by the CPU's microarchitecture can result in information leakage across virtual machines. For instance, cache attacks that exploit access time variations when retrieving data from the cache or the memory are a powerful tool to extract information from a co-located virtual machine. In this talk, we present several methods of how to exploit cache-based side channels across VM boundaries. It will be shown how the Flush+Reload and Prime and Probe attack techniques can be applied to extract sensitive information from a co-located VM across cores, including information about used cryptographic libraries, but also more fine-grain information such as AES keys. Potential mitigation techniques to prevent these kind of attacks are also discussed. This talk is based on joint work with Gorka Irazoqui, Mehmet Sinn Inci, Berk Gulmezoglu and Berk Sunar. (Full Announcement)


Latest News:

Exchange student from the Jean Monnet University in Saint-Etienne, France, visits CERG

Cédric Marchand, an exchange PhD student from Laboratoire Hubert Curien at the Jean Monnet University in Saint-Etienne, France, is visiting CERG in the period from August 31, 2015 to November 30, 2015. He is working on his PhD Thesis devoted to protecting integrated circuits against counterfeiting and theft of intellectual property. His dissertation work is a part of a larger funded project called SALWARE (SALutary hardWARE design to fight against integrated circuit counterfeiting and theft). His supervisor is Dr. Lilian Bossuet. (08/31/2015)


Dr. Gaj and Dr. Kaps received funding from McQ Inc and the Department of Defense.

Dr. Gaj and Dr. Kaps received $125K from McQ Inc. and the Department of Defense for their project entitled "Physical Unclonable Functions (PUFs) for Unique and Robust Encryption Key Generation (Phase II)." The period of performance is July 1, 2015 through August 8, 2016. (08/28/2015)


William Diehl passed the Research Qualifying Exam

William Diehl passed the PhD Research Qualifying Exam (RQE) on August 27, 2015. As a part of the exam, he presented his paper entitled "RTL Implementation of a Boolean Masking Scheme for the SCREAM Authenticated Cipher". The members of his RQE Committee included Dr. Gaj, Dr. Kaps, and Dr. Homayoun. (08/28/2015)


Ahmad Salman defended his PhD Thesis Proposal

Ahmad Salman defended his PhD Thesis Proposal entitled "Public Key Cryptography Using Hardware/Software Co-design for the Internet of Things," on July 31, 2015. The members of his dissertation committee include Dr. Kaps (Chair), Dr. Gaj, Dr. Homayoun, and Dr. Stavrou. (08/01/2015)


John Pham defended his MS Thesis

John Pham defended his MS Thesis entitled "Development and Benchmarking of Cryptographic Implementations on Embedded Platforms," on July 31, 2015. Members of his Committee included: Dr. Kaps (Chair), Dr. Gaj, and Dr. Lorie. After graduation, John will pursue a career as a Software Engineer at Orbital ATK. (08/01/2015)


Harsh Vachharajani defended his MS Thesis

Harsh Vachharajani defended his MS Thesis entitled "Implementation and Simulation of Secure Sockets Layer (SSL) in Windows Presentation Foundation," on July 30, 2015. Members of his Committee included: Dr. Gaj (Chair), Dr. Jones, and Dr. Simon. After graduation, Harsh will pursue a career as an Application Security Software Consultant at Deloitte in Arlington, Virginia. (07/31/2015)


Yamini Ravishankar defended her MS Thesis

Yamini Ravishankar defended her MS Thesis entitled "PUFs - An Extensive Survey," on July 28, 2015. Members of her Committee included: Dr. Kaps (Chair), Dr. Gaj, and Dr. Berry. After graduation, Yamini will pursue a career at Intel in Folsom, California. (07/29/2015)


Dr. Kaps served as a Panelist at the Lightweight Cryptography Workshop 2015

Dr. Kaps attended the Lightweight Cryptography Workshop 2015, organized by NIST on July 20-21, 2015, where he served as one of the panelists during the discussion on Lightweight Crypto Standardization. The other panelists included: Matt Robshaw (Impinj), Dan Shumow (Microsoft Research), and Douglas Shors (NSA). The discussion was moderated by Meltem Sonmez Turan (NIST). (07/22/2015)


Dr. Kaps gave a seminar at WPI

Dr. Kaps gave a seminar, entitled "Comparison of Multi-Purpose Cores of Keccak and AES on FPGAs" at Worcester Polytechnic Institute on July 3, 2015. The talk was part of the Seminar Series of the Vernam Group which is a cryptographic research group comprised of 5 faculty and several students. (7/8/15)


Dr. Gaj spoke at CryptArchi 2015

Dr. Gaj gave two talks at the 13th CryptArchi workshop on cryptographic architectures embedded in reconfigurable devices, held in Leuven, Belgium on June 28-July 1, 2015. His talks were entitled "Toward a Universal High-Speed Interface for Authenticated Ciphers," and "C vs. VHDL: Comparing Performance of CAESAR Candidates Using High-Level Synthesis on Xilinx FPGAs". (07/01/2015)


Dr. Gaj gave an invited talk at IRISA in Rennes, France

Dr. Gaj gave an invited talk, entitled "From C to Hardware: Toward Using High-Level Synthesis for Hardware Benchmarking of Candidates in Cryptographic Contests," at IRISA (Institute for Research in IT and Random Systems) in Rennes, France, on June 26, 2015. The talk was a part of a series of Seminars on Security of Embedded Electronic Systems, hosted by Dr. Arnaud Tisserand (CNRS, IRISA) and Dr. Benoît Gérard (DGA-MI, IRISA). (06/27/2015)


Dr. Gaj and Dr. Kaps received funding from NIST

Dr. Gaj and Dr. Kaps received $500K from the Department of Commerce (NIST) for their project "Post-Quantum Public Key Cryptosystems." The period of performance is June 1, 2015 through May 31, 2018. (06/23/2015)


Bilal Habib defended his PhD Thesis Proposal

Bilal Habib defended his PhD Thesis Proposal, entitled "Design, Implementation and Analysis of Efficient FPGA based Physical Unclonable Functions,” on June 22, 2015. The members of his dissertation committee include Dr. Gaj (co-Chair), Dr. Kaps (co-Chair), Dr. Homayoun, and Dr. Rangwala. (06/23/2015)


Dr. Gaj is a member of the Program Committees of CHES 2015 and LightSec 2015

Dr. Gaj is a member of the Program Committees for the following workshops:

Majority of student members of CERG have contributed their time and expertise serving as sub-reviewers for the aforementioned workshops.(06/01/2015)


Dr. Gaj serves as a co-chair of the special track at ReConFig 2015

Dr. Gaj and Dr. Tim Güneysu from Ruhr University Bochum, Germany, are co-chairs of the special track on Reconfigurable Computing for Security and Cryptography at the 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, to be held at Mayan Riviera, Mexico, on Dec. 7-9, 2015. (05/15/2015)


Members of CERG attended HOST 2015

Dr. Gaj, Dr. Kaps, Bilal Habib, and William Diehl attended HOST 2015, the IEEE International Symposium on Hardware-Oriented Security and Trust, held in Washington D.C., on May 5-7, 2015. (05/08/2015)


Ekawat Homsirikamol and Dr. Gaj spoke at ARC 2015

Ekawat Homsirikamol ("Ice") and Dr. Gaj attended the 11th International Symposium on Applied Reconfigurable Computing, ARC 2015, hosted by Ruhr-Universität Bochum on April 13-17, 2015. Ekawat gave the presentation entitled "Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study," and Dr. Gaj gave the talk "Efficient SR-Latch PUF." Additionally, as a part of this conference, Ekawat and Dr. Gaj attended Xilinx workshop entitled: Advanced Embedded System Design on Zynq using Vivado. (04/17/2015)


Dr. Gaj and Ahmed Ferozpuri attended Workshop on Cybersecurity in a Post-Quantum World

Dr. Gaj and Ahmed Ferozpuri attended Workshop on Cybersecurity in a Post-Quantum World, organized by NIST in Gaithersburg, MD, on April 2-3, 2015. (04/04/2015)


Dr. Kaps gave a seminar at Fraunhofer AISEC

Dr. Kaps gave a seminar, entitled "Comparison of Multi-Purpose Cores of Keccak and AES on FPGAs" at Fraunhofer Institute for Applied and Integrated Security (AISEC) in Munich, Germany on March 16, 2015. The presentation was also attended by students of the Institute for Security in Information Technology of the Technische Universität München. The institute is chaired by Dr. Sigl. (03/17/2015)


Dr. Kaps attended DATE 2015

Dr. Kaps will attend the 18th Design Automation and Test in Europe conference, DATE 2015, held in Grenoble, France, on March 9 - 13, 2015. As a part of this conference, he gave an interactive presentation, entitled "Comparison of Multi-purpose Cores of Keccak and AES," based on the paper co-authored with Panasayya Yalla and Ekawat Homsirikamol. (03/17/2015)


Rajesh Velegalati defended his PhD Thesis

Rajesh Velegalati defended his PhD Thesis entitled "Developing an Integrated Environment for Detecting and Mitigating Side-channel and Fault attacks on Hardware Platforms," on February 2nd, 2015. The members of his dissertation committee included Dr. Kaps (Chair), Dr. Gaj, Dr. Nelson, and Dr. Stavrou. (02/21/2015)


Panasayya Yalla defended his PhD Thesis Proposal

Panasayya Yalla defended his PhD Thesis Proposal entitled "Methodology for Developing Lightweight Architectures for FPGAs," on January 9, 2015. The members of his dissertation committee include Dr. Kaps (Chair), Dr. Gaj, Dr. Mark, and Dr. Simon. (02/21/2015)


Dr. Gaj and Dr. Kaps attended SaTCPI 2015

Dr. Gaj and Dr. Kaps attended the National Science Foundation Secure and Trustworthy Cyberspace (SaTC) Principal Investigators' Meeting, SaTCPI 2015, held on January 5-7, 2015, in Arlington, VA. (02/21/2015)


Latest Publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • B. Habib, K. Gaj, and J.-P. Kaps, Efficient SR-latch PUF, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 205-216, Apr., 2015 [Bibtex]
  • E. Homsirikamol and K. Gaj, Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 217-228, Apr, 2015 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe Conference Exhibition DATE 2015, Mar, 2015 [Bibtex]
  • E. Homsirikamol and K. Gaj, Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study., 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2014, IEEE, pages 1–8, Dec., 2014 [Bibtex]
  • P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wojcik, ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption, Cryptographic Hardware and Embedded Systems, CHES 2014, LNCS, volume 8731, Springer Berlin Heidelberg, pages 392–413, Sep., 2014 [Bibtex]
  • M. Rogawski, E. Homsirikamol, and K. Gaj, A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs, 24th International Conference on Field Programmable Logic and Applications – FPL 2014, IEEE, pages 1–8, Sep., 2014 [Bibtex]