CERG Support of CAESAR

SHARCS 2012

CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Members of CERG have developed the CAESAR Hardware API for authenticated ciphers, approved by the CAESAR Committee. Our group has also developed comprehensive Development Package, including VHDL and Python code common for all candidates, and the corresponding Implementer's Guide. CERG has contributed optimized high-speed RTL implementations AES-GCM, 11 Round 3 and 24 Round 2 CAESAR Candidates. Members of our team have also conducted comprehensive FPGA benchmarking of all Round 3 and all Round 2 implementations, submitted by 16 hardware design teams from all over the world. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. The summary of the Round 2 RTL benchmarking effort and an alternative benchmarking methodology based on High-Level Synthesis were presented at DIAC 2016. The summary of the Round 3 RTL benchmarking effort was posted on the CAESAR page of the ATHENa website in August 2017. Additionally, two current members (Ice and Dr. Gaj) and one former member of CERG (Marcin) were co-authors of ICEPOLE, a high-speed, hardware-oriented Round 2 CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) could be used to provide high data processing rates.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Seminars:

High-Speed Hardware Implementations of Post-Quantum Cryptography Multivariate Signature Schemes

Ahmed Ferozpuri, ECE MS Defense
Date: Wednesday, December 6, 10:30 AM - 12:00 PM
Location: Engineering Building, Room 2901

Multivariate cryptosystems belong to the five most promising families of post-quantum cryptography (PQC) schemes. Among them, the Unbalanced Oil and Vinegar (UOV) and the Rainbow signature schemes have been extensively studied since 1999 and 2005, respectively. Read More ...


Methodology for Developing Lightweight Architectures for FPGAs

Panasayya Yalla, ECE PhD Defnese
Date: Friday, December 1, 1:30 PM - 3:00 PM
Location: Engineering Building, Room 4801

Until now, application specific integrated circuits (ASICs) are the main platform for lightweight cryptography because of their low power consumption and good performance. However, their complex design cycle and very high non-recurring engineering cost limit them to high volume applications. Read More ...


Latest News:

William Diehl gave a presentation at FPL 2017

William Diehl attended the 27th International Conference on Field-Programmable Logic and Applications, FPL 2017, held in Ghent, Belgium, on September 4-8, 2017. As part of this conference, William gave a short talk and presented a poster, entitled "Comparison of Hardware and Software Implementations of Selected Lightweight Block Ciphers," based on the paper co-authored with Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps and Kris Gaj. Additionally, William attended the workshop FPGAs for Software Programmers, FSP 2017, co-located with FPL. (09/08/2017)


Sanjay Deshpande spoke at DSD 2017

Sanjay Deshpande spoke at the Euromicro Conference on Digital System Design, held in Vienna, Austria, on August 30-September 1, 2017. He delivered an oral presentation entitled "Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates," co-authored with Kris Gaj. (09/02/2017)


CERG welcomed new members

At the end of August 2017, CERG welcomed new members: Viet Ba Dang who completed his BS degree in Electronics and Telecommunication at the Danang University of Science and Technology in Vietnam in 2016, Duc Tri Nguyen who completed his B.Eng in Computer Engineering at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Vietnam in 2015, and Chaitanya Neelamraju, who earned his Bachelor of Technology degree in Electronics & Communication Engineering (ECE) from Mahaveer Institute of Science & Technology, JNTUH in India in 2016. Viet and Duc will pursue their PhD degrees, and Chaitanya will work on his Master's thesis, all under the supervision of Dr. Gaj, with the focus on the area of post-quantum cryptography. (09/01/2017)


Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology:

Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Ho Chi Minh City, Vietnam, on Aug. 16, 2017. His presentation was entitled "From AES to Post-Quantum Cryptography: FPGA Battles of Cryptographic Algorithms". It was attended by more than 30 faculty members and students from the Faculty of Computer Science and Engineering of the Bach Khoa University. (08/17/2017)


Presentation summarizing benchmarking of Round 3 CAESAR Candidates

The GMU Benchmarking Team has published and announced a comprehensive presentation, entitled "Benchmarking of Round 3 CAESAR Candidates in Hardware: Methodology, Designs & Results," made available at the CAESAR page of the ATHENa website. The GMU Team has contributed high-speed RTL implementations of AES-GCM and 11 Round 3 CAESAR Candidates. (08/11/2016)


Ahmad Salman defended his PhD Thesis

Ahmad Salman defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Kaps (Chair), Dr. Gaj , Dr. Homayoun , and Dr. Stavrou. In the middle of August 2017, Ahmad joined James Madison University in Harrisonburg, VA, as a tenure-track Assistant Professor. (2017/08/15)


Malik Umar Sharif defended his PhD Thesis

Malik Umar Sharif defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun , and Dr. Simon. Since March 2017, Umar has been already working as an FPGA Engineer at ixia, near Portland, OR. (2017/08/15)


Rabia Shahid defended her PhD Thesis

Rabia Shahid defended her PhD Thesis, entitled "A New Approach to the Development of Coprocessors for Pairing-based Cryptosystems," on July 31, 2017. The members of her dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun, and Dr. Albanese. In mid-August 2017, Rabia joined ixia, near Portland, OR, as an FPGA Engineer. (2017/08/15)


Dr. Gaj and Dr. Kaps attended PQCrypto 2017

Dr. Gaj and Dr. Kaps attended the 8th International Conference on Post-Quantum Cryptography, PQCrypto 2017, held in Utrecht, the Netherlands, June 26-28, 2017. During the Recent Result Session on June 26, chaired by Dr. Wouter Castryck, Dr. Gaj delivered a short presentation entitled "High-Speed Hardware for NTRUEncrypt-SVES: Lessons Learned", co-authored with Malik Umar Sharif. Additionally, Dr. Kaps attended a week-long Summer School on Post-Quantum Cryptography (organized by the H2020 project PQCRYPTO), and Dr. Gaj attended a two-day Executive School on Post-Quantum Cryptography (organized by the H2020 project ECRYPT-CSA). Both schools were held at the Technische Universiteit Eindhoven on June 19-23 and June 22-23, 2017, respectively. (06/29/2017)


Dr. Gaj spoke at CryptArchi 2017

Dr. Gaj spoke at the 15th International Workshop on Cryptographic Architectures Embedded in Logic Devices, CryptArchi 2017, held in Smolenice, Slovakia, on June 18-21, 2017. He delivered a talk entitled "Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems," co-authored with Malik Umar Sharif and Ahmed Ferozpuri. (06/22/2017)


Dr. Gaj spoke at the Workshop on Hardware Benchmarking 2017

Dr. Gaj spoke at the Workshop on Hardware Benchmarking, held in Bochum, Germany, on June 7, 2017. He delivered an invited talk entitled "Fair and Efficient Hardware Benchmarking of Candidates in Cryptographic Contests". (06/07/2017)


Rabia Shahid spoke at RAW 2017

Rabia Shahid spoke at the 24th Reconfigurable Architecture Workshop - RAW 2017, co-located with the 31st Annual IEEE International Parallel and Distributed Processing Symposium - IEEE IPDPS 2017, held in Orlando, Florida, on May 29-June 2, 2017. She delivered a talk entitled "A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems," based on the paper co-authored with Ted Winograd and Dr. Gaj. (06/01/2017)


Farnoud Farahmand earned internship at Google

Farnoud Farahmand has earned the position of the Hardware Engineer Intern at Google in Mountain View, CA, to be held between May 30 and August 25, 2017. (05/30/2017)


Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards

CERG Members, Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards, handed to them by the ECE Department Chair, Prof. Monson Hayes, during the ECE Convocation Reception on May 18, 2017. Here is a photo of all awardees together with their academic advisor Dr. Gaj. (05/19/2017)


William Diehl qualified to the finals of the 3M Thesis Competition

William Diehl qualified to the finals of the 3-Minute Thesis competition. The preliminary round was held on March 3, 2017, in the HUB Rooms 4 & 5. 48 GMU doctoral students entered the contest, of whom 20 were from the Volgenau School of Engineering. Each contestant had three minutes (and one Powerpoint slide) to explain his/her research to a general audience. William was the only student representing CERG. The finals were held on Saturday, March 25, at Mason's Arlington Campus. They were part of the Mason Graduate Interdisciplinary Conference. An article about the competition, with a quote from William, was written by Martha Bushong, and published in News at Mason. The full video of his talk is available here. (03/06/2017)


Dr. Gaj's research featured in the Spring 2017 ECE Newsletter

Dr. Gaj's research has been featured in the Spring 2017 ECE Newsletter. The article about Dr. Gaj is called "Battles for Cryptographic Algorithms". (02/11/2017).


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • S. Deshpande and K. Gaj, Analysis and inner-round pipelined implementation of selected parallelizable CAESAR competition candidates, 19th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, Aug., 2017 [Bibtex]
  • B. Habib, J.-P. Kaps, and K. Gaj, Implementation of efficient SR-latch PUF on FPGA and SoC devices, Microprocessors and Microsystems, volume 53, pages 92-105, Aug., 2017 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of selected CAESAR round two authenticated ciphers, Microprocessors and Microsystems, volume 52, pages 202-218, July, 2017 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Microprocessors and Microsystems, volume 51, pages 239-251, June, 2017 [Bibtex]
  • R. Shahid, T. Winograd, and K. Gaj, A generic approach to the development of coprocessors for Elliptic Curve Cryptosystems, 24th Reconfigurable Architectures Workshop, RAW 2017, Orlando, FL, May, 2017 [Bibtex]
  • C. Marchand, L. Bossuet, and K. Gaj, Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes, International Journal of Circuit Theory and Applications, volume 45, pages 274-291, Feb., 2017 [Bibtex]
  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]