SHARCS 2012 in Washington D.C.


CERG was an organizer of SHARCS 2012 - Special-Purpose Hardware for Attacking Cryptographic Systems workshop held in the Washington Marriott Hotel on March 17-18, 2012. Dr. Kaps served as a general chair of the workshop, and Dr. Gaj was one of the two co-chairs. Graduate students from CERG provided technical and logistic support during the event. This edition of SHARCS had more than 70 participants from 19 countries of 5 continents. The slides of all presentations and the workshop record are posted on the SHARCS 2012 website. An extensive record of the entire series, including all slides and papers from the previous workshops, is available at (3/19/12)

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Towards Automatic Application and Verification of Countermeasures Against Physical Attacks

Francesco Regazzoni, ALaRI Institute of University of Lugano, Switzerland
Date: Monday, May 11th, 3:00 PM - 4:00 PM
Location: Engineering Building, Room 3507

Physical attacks exploit the physical weaknesses of cryptographic devices to reveal the secret information stored on them. Countermeasures against these attacks are often considered only in the later stages of the full design flow, and applied manually by designers with strong security expertise. This approach, however, negatively affects the robustness, the cost, and the production time of secure devices. In view of this increasingly relevant problem, it is crucial to address the design challenges associated with the proliferation of physical attacks, developing a methodology to automate the design and the verification of secure embedded systems. This talk focuses on one type of physical attacks, the differential power analysis (DPA), and presents the design and the implementation of the infrastructure needed to enable the automatic application and verification of DPA countermeasures. (Full Announcement)

Latest News:

Ekawat Homsirikamol and Dr. Gaj spoke at ARC 2015

Ekawat Homsirikamol ("Ice") and Dr. Gaj attended the 11th International Symposium on Applied Reconfigurable Computing, ARC 2015, hosted by Ruhr-Universität Bochum on April 13-17, 2015. Ekawat gave the presentation entitled "Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study," and Dr. Gaj gave the talk "Efficient SR-Latch PUF." Additionally, as a part of this conference, Ekawat and Dr. Gaj attended Xilinx workshop entitled: Advanced Embedded System Design on Zynq using Vivado. (04/17/2015)

Dr. Kaps attended DATE 2015

Dr. Kaps will attend the 18th Design Automation and Test in Europe conference, DATE 2015, held in Grenoble, France, on March 9 - 13, 2015. As a part of this conference, he gave an interactive presentation, entitled "Comparison of Multi-purpose Cores of Keccak and AES," based on the paper co-authored with Panasayya Yalla and Ekawat Homsirikamol. (04/17/2015)

Rajesh Velegalati defended his PhD Thesis

Rajesh Velegalati defended his PhD Thesis entitled "Developing an Integrated Environment for Detecting and Mitigating Side-channel and Fault attacks on Hardware Platforms," on February 2nd, 2015. The members of his dissertation committee included Dr. Kaps (Chair), Dr. Gaj, Dr. Nelson, and Dr. Stavrou. (02/21/2015)

Panasayya Yalla defended his PhD Thesis Proposal

Panasayya Yalla defended his PhD Thesis Proposal entitled "Methodology for Developing Lightweight Architectures for FPGAs," on January 9, 2015. The members of his dissertation committee include Dr. Kaps (Chair), Dr. Gaj, Dr. Mark, and Dr. Simon. (02/21/2015)

Dr. Gaj and Dr. Kaps attended SaTCPI 2015

Dr. Gaj and Dr. Kaps attended the National Science Foundation Secure and Trustworthy Cyberspace (SaTC) Principal Investigators' Meeting, SaTCPI 2015, held on January 5-7, 2015, in Arlington, VA. (02/21/2015)

Ekawat Homsirikamol spoke at ReConFig 2014

Ekawat Homsirikamol ("Ice") spoke at the 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2014, held in Cancun, Mexico, on December 8-10, 2014. Ekawat gave the talk entitled "Can High-Level Synthesis Compete Against a Hand-Written Code in the Cryptographic Domain? A Case Study." (02/21/2015)

Exchange student from TUM, Germany, visits CERG

Stefan Theil an exchange student from Technische Universität München (TUM) is visiting CERG in the period from November 1, 2014 to April 30, 2015. He is working on his Master's Thesis in the area of countermeasures against side-channel attacks, under the joint supervision of Prof. Sigl, Dr. De Santis, and Dr. Kaps.

Dr. Gaj and Dr. Szczypiorski gave talks at Virginia Tech

On October 8, 2014, Dr. Gaj, Dr. Szczypiorski, Ekawat Homsirikamol, and Malik Umar Sharif visited the Configurable Computing Lab at Virginia Tech, led by Prof. Peter Athanas. During this visit, Dr. Gaj gave the talk entitled "Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools," and Dr. Szczypiorski gave the presentation entitled "Information Hiding in Communication Networks." Additionally, a few of Virginia Tech students and Dr. Kepa, a postdoc in Configurable Computing Lab, gave demos of their recent research projects. (02/21/2015)

Dr. Gaj attended CHES 2015

Dr. Gaj attended the 16th Workshop on Cryptographic Hardware and Embedded Systems, CHES 2014, held in Busan, South Korea, on September 23-26, 2014. As a part of this workshop Dr. Morawiecki from Polish Academy of Sciences and University of Commerce in Kielce, Poland, gave the talk entitled ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption Scheme, co-authored by three members of the CERG team. (02/21/2015)

Dr. Gaj gave an invited talk at Sungkyunkwan University

Dr. Gaj gave an invited talk, entitled "Battles of Cryptographic Algorithms: From AES to CAESAR in Software & Hardware," in the Mathematics Department at the Sungkyunkwan University in Suwon, South Korea, on September 22, 2014. Additionally, on September 21, 2014, he visited Mason Korea, a part of the Global University Campus located in Songdo, near the Incheon International Airport in Korea, shared with the University of Utah, Belgium's Ghent University, and the State University of New York (SUNY) at Stony Brook University. (02/21/2015)

Visiting Professor from Warsaw University of Technology, Poland

In September and October 2014, CERG was hosting a distinguished visitor, Dr. Krzysztof Szczypiorski from Warsaw University of Technology in Warsaw, Poland, a world-renowned expert in the areas of steganography, network security, digital forensics, open-source intelligence, and wireless communications. Dr. Szczypiorski is the founder of Network Security Group at WUT and project focused on network steganography and steganalysis. He is the author or the co-author of 180+ publications including 130+ papers and 50+ invited talks. As a part of his visit at GMU, Dr. Szczypiorski gave the ECE Seminar, entitled "Trends in Network Steganography," taught two invited lectures of ECE 646, supervised several student projects, and met with multiple faculty members working in the areas of cyber security, cryptography, steganography, privacy, and computer forensics. The established collaboration is likely to lead to future joint research projects and publications. (02/21/2015)

Latest Publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe Conference Exhibition DATE 2015, Mar, 2015 [Bibtex]
  • E. Homsirikamol and K. Gaj, Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study., 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2014, IEEE, pages 1–8, Dec., 2014 [Bibtex]
  • P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wojcik, ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption, Cryptographic Hardware and Embedded Systems, CHES 2014, LNCS, volume 8731, Springer Berlin Heidelberg, pages 392–413, Sep., 2014 [Bibtex]
  • M. Rogawski, E. Homsirikamol, and K. Gaj, A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs, 24th International Conference on Field Programmable Logic and Applications – FPL 2014, IEEE, pages 1–8, Sep., 2014 [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, FPGA PUF based on programmable LUT delays, 2013 Euromicro Conference on Digital System Design (DSD), pages 697–704, 2013 [accepted version, pdf] [Bibtex]
  • R. Velegalati, K. Shah, and J.-P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, 2013 Euromicro Conference on Digital System Design (DSD), pages 947–954, 2013 [Bibtex]
  • M. Rogawski, K. Gaj, and E. Homsirikamol, A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl, Microprocessors and Microsystems, volume 37, number 6-7, pages 572-582, 2013 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS), June, 2013, Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI 2013 [pdf] [Bibtex]