CERG Support of CAESAR

SHARCS 2012

CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Members of CERG have developed the CAESAR Hardware API for authenticated ciphers, approved by the CAESAR Committee. Our group has also developed comprehensive Development Package, including VHDL and Python code common for all candidates, and the corresponding Implementer's Guide. CERG has contributed optimized high-speed RTL implementations AES-GCM, 11 Round 3 and 24 Round 2 CAESAR Candidates. Members of our team have also conducted comprehensive FPGA benchmarking of all Round 3 and all Round 2 implementations, submitted by 16 hardware design teams from all over the world. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. The summary of the Round 2 RTL benchmarking effort and an alternative benchmarking methodology based on High-Level Synthesis were presented at DIAC 2016. The summary of the Round 3 RTL benchmarking effort was posted on the CAESAR page of the ATHENa website in August 2017. Additionally, two current members (Ice and Dr. Gaj) and one former member of CERG (Marcin) were co-authors of ICEPOLE, a high-speed, hardware-oriented Round 2 CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) could be used to provide high data processing rates.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Seminars:

Enabling a Control System Approach to Side-Channel and Fault Attacks

Ryan Matthew Carter, ECE MS Defense
Date: Wednesday, December 5th, 3:00 pm - 4:00 pm
Location: Engineering Building, Room 3507

As the number of embedded devices continues to grow, attacks that require physical access to the device become more plausible. Two sub-classifications of these attacks, Side-Channel Attacks (SCA) and Fault attacks, necessitate the attacker to be familiar with the target implementation. Side-Channel Attacks exploit information leaked by the target device to discover secret cryptographic keys. Fault attacks act upon the system to induce error in device operation that may result in information leakage or improper execution. The error produced by the attack is dependent on the method used to inject the fault. This paper discusses some of the advances in SCAs and Fault Attacks and proposes a control system approach to these classes of attacks. The result of the research is a System on a Chip (SOC) for measuring power consumption, analyzing results, and refining measurement as a feedback loop.


Job Announcements:

GRA Positions in Post-Quantum Cryptography

CERG is seeking qualified candidates for multiple Graduate Research Assistant positions in the area of efficient implementations of Post-Quantum Cryptosystems, side-channel attacks targeting these cryptosystems, and countermeasures against such attacks. The desired qualifications include strong mathematical background in algebra and number theory, experience in hardware design using hardware description languages, and knowledge of C and scripting languages, such as Python. Additional experience in Magma or SageMath, ASIC or FPGA design, software/hardware codesign, High-Level Synthesis, embedded software development, and Linux operating system is a plus.

GRA Position in Lightweight Cryptography

CERG is seeking qualified candidates for a Graduate Research Assistant position in the area of efficient and secure implementations of Lightweight Cryptography. The desired qualifications include experience in embedded systems, knowledge of C, assembly and scripting languages, hardware design using hardware description languages, Linux operating system, and strong experimental skills. Additional experience in side-channel and fault attacks, countermeasures against these attacks, ASIC or FPGA design, software/hardware codesign, embedded software development, and/or circuit/PCB design is a plus.

All positions are open starting in January 2019. Qualified candidates should apply to the ECE PhD program at George Mason University by October 15, 2018, indicating Dr. Gaj and/or Dr. Kaps as possible future advisors. In parallel, an earlier e-mail contact with Dr. Gaj and/or Dr. Kaps is highly recommended.


Latest News:

Dr. Gaj and Dr. Kaps awarded NSF grant for research on Side-Channel Attack Countermeasures for Post-Quantum Cryptography

Dr. Gaj and Dr. Kaps were awarded a grant from the National Science Foundation for their project "SaTC: CORE: Medium: Collaborative: Countermeasures Against Side-Channels Attacks Targeting Hardware and Embedded System Implementations of Post-Quantum Cryptographic Algorithms". The period of performance is October 1, 2018 through September 30, 2022. The first year funding is $105,571, and the anticipated total funding $450,000. This project is a joint effort with the research groups of Dr. Reza Azarderakhsh and Dr. Mehrdad Nojoumian from Florida Atlantic University, and of Dr. Mehran Mozaffari Kermani from University of South Florida. GMU serves a lead organization for this effort. The total anticipated funding for all three universities is $1.2M. (09/08/2018)


Dr. Kaps and Dr. Gaj awarded NIST grant for research on Lightweight Cryptography

Dr. Kaps and Dr. Gaj were awarded a grant from the U.S. Department of Commerce (NIST) for their project "Lightweight Cryptography in Hardware and Embedded Systems". The period of performance is September 1, 2018 through August 31, 2021. The first year funding is $164,694, and the anticipated total funding $499,970. This project is a joint effort with the research group of Dr. William Diehl from Virginia Tech. (09/02/2018)


Dr. Gaj and Dr. Kaps awarded NIST grant for research on Post-Quantum Cryptography

Dr. Gaj and Dr. Kaps were awarded a grant from the U.S. Department of Commerce (NIST) for their project "Post-Quantum Cryptography in Hardware and Embedded Systems". The period of performance is September 1, 2018 through August 31, 2021. The first year funding is $161,918, and the anticipated total funding $500,000. (09/02/2018)


CERG becomes a part of CHEST

CERG has joined CHEST: Center for Hardware and Embedded Systems Security and Trust, developed as a part of the NSF Industry-University Cooperative Research Centers Program. CHEST, launched in May 2018, includes research groups from the following six universities: George Mason University, Northeastern University, the University of Cincinnati, the University of Connecticut, the University of Texas at Dallas, and the University of Virginia. The research activities of CHEST will cover security and trust at the following levels: systems/application, architectural and board, embedded-device, FPGA and ASIC, and circuit (including analog, RF, and digital). At GMU, the following research groups have become a part of CHEST: Accelerated, Secure, and Energy-Efficient Computing Lab (ASEEC), led by Dr. Homayoun; Green, Accelerated, and Trustworthy Engineering (GATE) Lab, led by Dr. Sasan, and Cryptographic Engineering Research Group (CERG), led by Drs. Gaj and Kaps. The planning meeting of CHEST took place on August 23-24, 2018, at George Mason University, with the participation of all collaborating universities, as well as representatives of National Science Foundation, Air Force Research Lab, and about 30 companies and industry/government labs. During the planning meeting Dr. Gaj gave the project proposal presentation entitled "Post-Quantum Cryptography in Hardware and Embedded Systems," and student members of CERG presented two posters about recent research activities of CERG. (2018/09/02)


Ahmed Ferozpuri passed the Research Qualifying Exam

Ahmed Ferozpuri passed the PhD Research Qualifying Exam (RQE) on August 31, 2018. As a part of the exam, he presented his paper entitled "High-Speed FPGA Implementation of the Rainbow Signature Scheme". The members of his RQE Committee included Dr. Gaj (Chair), Dr. Kaps, and Dr. Sasan. (2018/09/01)


Ted Winograd defended his PhD Thesis Proposal

Ted Winograd defended his PhD Thesis Proposal, entitled "A New Approach to the Development of Cryptographic Hardware Based on Specialized Computer-Aided Design Tools," on August 21, 2018. Members of his dissertation committee include Dr. Gaj (Chair), Dr. Homayoun (co-Chair), Dr. Kaps, and Dr. Ammann. (2018/08/22)


Dr. Gaj and Dr. Kaps gave presentations at CryptArchi 2018

Dr. Gaj and Dr. Kaps attended CryptArchi 2018, held in Guidel-Plages near Lorient, France, on June 17-20, 2018. Dr. Gaj gave a talk entitled "Post-Quantum Cryptography in Reconfigurable Hardware: Challenges, Opportunities, and State-of-the-Art ," and Dr. Kaps delivered a presentation entitled "Evaluation of DPA Protected Implementations of CAESAR Finalists ACORN and Ascon and other Candidates". (06/21/2018)


Dr. Gaj organized a special session and spoke at GLSVLSI 2018

Dr. Gaj attended the 28th ACM Great Lakes Symposium on VLSI - GLSVLSI 2018, held in Chicago, IL, on May 23-25, 2018. He served as an organizer of the special session on "Implementing and Benchmarking Post-Quantum Cryptography in Hardware," and gave a talk entitled "Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware". (05/26/2018)


Student members of CERG received special departmental awards

During the ECE Departmental Awards Ceremony held on May 17, 2018, several members of CERG were recognized with the following awards: William Diehl received the Outstanding Academic Achievement Award for Ph.D. students, Ahmad Salman, Rabia Shahid, Malik Umar Sharif, and Panasayya Yalla received Chairman's Awards, and Ahmed Ferozpuri received the Special Recognition Award. (05/18/2018)


Ahmed Ferozpuri spoke at ICMC 2018

Ahmed Ferozpuri spoke at the International Cryptographic Module Conference, held in Ottawa, Ontario, Canada, on May 8-11, 2018. He delivered an oral presentation entitled "Using FPGAs in the Cloud for Decentralized Trusted Execution". He also attended the pre-conference workshops, held on Tuesday, May 8. (05/11/2018)


Farnoud Farahmand spoke at FCCM 2018

Farnoud Farahmand spoke at the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, held in Boulder, CO, on April 29 - May 1, 2018. He delivered an oral presentation entitled "Improved Lightweight Implementations of CAESAR Authenticated Ciphers," co-authored with William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. (05/02/2018)


William Diehl defended his PhD Thesis

William Diehl defended his PhD Thesis, entitled "Comparing Costs of Protecting Secret Key Ciphers Against Differential Power Analysis," on April 24, 2018. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Sasan, and Dr. Ammann. The thesis was co-advised by Dr. Gaj and Dr. Kaps. In March 2018, William accepted the tenure-track assistant professor position at Virginia Tech in Blacksburg, VA. (04/25/2018)


CERG Team gave two demos and one poster presentation at HOST 2018

CERG Team, including Abubakr Abdulgadir, Ryan Carter, William Diehl, Raghurama Velagala, Dr. Kaps, and Dr. Gaj, attended the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, held in McLean, VA, on April 30-May 4, 2018. During this conference, our team gave two demos entitled: Flexible, Opensource workBench fOr Side-channel analysis (FOBOS) and eXtended eXternal Benchmarking eXtension (XXBX). Additionally, William Diehl gave the poster presentation entitled "Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers," co-authored with Abubakr Abdulgadir, Farnoud Farahmand, Dr. Kaps, and Dr. Gaj. Finally, Michael Tempelmeier from Technical University of Munich (TUM) gave the talk entitled "The CAESAR-API in the Real World - Towards a Fair Evaluation of Hardware CAESAR Candidates," co-authored with Dr. Kaps. (04/20/2018)


CERG Team attended CBC 2018, PQCrypto 2018, and First PQC Standardization Conference

CERG Team, including Viet Dang, Ahmed Ferozpuri, Duc Nguyen, Dr. Gaj, and Dr. Kaps, attended a sequence of the following three conferences: The Sixth Code-Based Cryptography Workshop, CBC 2018, held on April 5-6, 2018; The Ninth International Conference on Post-Quantum Cryptography, PQCrypto 2018, held on April 9-11, 2018, and First PQC Standardization Conference, held on April 11-13, 2018. All conferences were located in Fort Lauderdale, FL. During the CBC 2018 workshop, Viet Dang gave a talk entitled "Hardware Implementation of the Code-based Key Encapsulation Mechanism using Dyadic GS Codes (DAGS)," co-authored with Dr. Gaj. During the Recent Results Session at the PQCrypto 2018 conference, Dr. Gaj, Ahmed Ferozpuri, and Viet Dang gave three short talks entitled, respectively, "PQC Hardware API & Fair Benchmarking of PQC," "High-Speed HW Implementation of the Multivariate Signature Schemes Unbalanced Oil and Vinegar (UOV), and Rainbow," and "Hardware Implementation of DAGS". (04/14/2018)


William Diehl and Dr. Gaj gave presentations at FPT 2017

William Diehl and Dr. Gaj attended the 2017 International Conference on Field-Programmable Technology, FPT 2017, held in Melbourne, Australia, on December 11-13, 2017. William Diehl gave an oral presentation entitled "Comparing the Cost of Protecting Selected Lightweight Block Ciphers Against Differential Power Analysis in Low-Cost FPGAs," based on the paper co-authored with Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. He also gave a poster presentation, entitled "A Light-Weight Hardware/Software Co-Design for Pairing-Based Cryptography with Low Power and Energy," based on the paper co-authored with Ahmad Salman and Jens-Peter Kaps. Dr. Gaj gave an oral presentation entitled "Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study", based on the paper co-authored with Ekawat Homsirikamol. He also gave a poster presentation entitled "Selection of an Error-Correcting Code for FPGA-based Physical Unclonable Functions," based on the paper co-authored with Brian Jarvis. After the main conference, William Diehl and Dr. Gaj attended the full-day workshop entitled "BAMBU: An open-source framework for research in high-level synthesis," presented by Fabrizio Ferrandi from Politecnico di Milano in Italy and Christian Pilato from Universita della Svizzera italiana (USI) in Switzerland. (12/14/2017)


CERG released HLS-ready C code of Round 3 CAESAR candidates

On December 11, 2017, CERG released HLS-ready C code of AES-GCM and 14 Round 3 CAESAR Candidates, targeting Vivado HLS. All implementations have been developed by Ekawat Homsirikamol (a.k.a. Ice) and demonstrated performance comparable with the performance of the corresponding Register-Transfer-Level implementations developed by multiple authors. The release of the code coincided with the presentation of the paper entitled "Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study", co-authored by Ekawat Homsirikamol and Kris Gaj. This project clearly demonstrated that a single designer can develop close-to-optimal implementations of multiple candidates, at the intermediate stages of the cryptographic competitions, and achieve very good correlation between the rankings of candidates implemented using the traditional manual Register-Transfer Level approach and the novel, more efficient High-Level Synthesis approach. (12/11/2017)


William Diehl and Panasayya Yalla gave presentations at ReConFig 2017

William Diehl and Panasayya Yalla attended the 2017 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, held in Cancun, Mexico, on December 4-6, 2017. William Diehl gave an oral presentation entitled "Side-channel Resistant Soft Core Processor for Lightweight Block Ciphers," based on the paper co-authored with Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. He also gave a poster presentation, entitled "Minerva: Automated Hardware Optimization Tool," based on the paper co-authored with Farnoud Farahmand, Ahmed Ferozpuri, and Kris Gaj. Panasayya Yalla gave an oral presentation entitled "A Scalable ECC Processor Implementation for High-Speed and Lightweight with Side-Channel Countermeasures", based on the paper co-authored with Ahmad Salman, Ahmed Ferozpuri, Ekawat Homsirikamol, Jens-Peter Kaps, and Kris Gaj. He also gave a poster presentation entitled "Evaluation of CAESAR Hardware API for Lightweight Implementations," based on the paper co-authored with Jens-Peter Kaps. (12/07/2017)


Ahmed Ferozpuri defended his Master's Thesis

Ahmed Ferozpuri defended his Master's Thesis entitled "High-Speed Hardware Implementations of Post-Quantum Cryptography Multivariate Signature Schemes," on December 6, 2017. Members of his Committee included: Dr. Gaj (Chair), Dr. Kaps, and Dr. Sasan. (12/07/2017)


CERG released Minerva

On December 5, 2017, CERG released Minerva - Automated Hardware Optimization Tool, used for optimization and benchmarking of VHDL and Verilog implementations, targeting most recent families of FPGA devices. Minerva supplements ATHENa, our older generation hardware benchmarking tool, which supports Xilinx ISE, Altera Quartus II, and Intel Quartus Prime toolsets. The first version of Minerva aims specifically at the Xilinx Vivado toolset and Xilinx reconfigurable devices at and beyond the Series 7 families: Virtex-7, Kintex-7, Artix-7, and Zynq-7000. Minerva is based on a heuristic optimization algorithm aimed at finding optimum requested clock frequency and the best optimization strategy (one out of multiple sets of tool options, predefined in Xilinx Vivado), leading to either optimal throughput or optimal throughput-to-area ratio. The release of Minerva coincided with the presentation of the paper entitled "Minerva: Automated Hardware Optimization Tool," co-authored by members of CERG (Farnoud Farahmand, Ahmed Ferozpuri, William Diehl, and Kris Gaj), at the 2017 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, held in Cancun, Mexico, on December 4-6, 2017. (12/05/2017)


CERG released the Development Package and Implementer's Guide for Hardware Implementations Compliant with the CAESAR Hardware API, v.2.0

On December 5, 2017, CERG released the substantially extended and updated version 2 of the Development Package for Hardware Implementations Compliant with the CAESAR Hardware API, supplemented with the corresponding Implementer's Guide. The main new features include 1) full support for the development of lightweight implementations, optimized for minimum area, power, and energy per bit, 2) extended support for the development of high-speed implementations, covering all Round 2 and Round 3 CAESAR candidates, except Keyak, optimized for maximum throughput/area and throughput, 3) improved support for experimental testing using FPGA boards, in applications with intermittent availability of input sources and output destinations. The release of this package and guide is aimed at a) simplifying and speeding-up any future hardware development efforts for authenticated ciphers, b) making the developed cores easier to integrate into real-world systems, and c) accelerating the remaining phases of the CAESAR candidate evaluation. (12/05/2017)


Panasayya Yalla defended his Ph.D. Thesis

Panasayya Yalla defended his Ph.D. Thesis entitled "Methodology for Developing Lightweight Architectures for FPGAs," on December 1, 2017. Members of his Committee included: Dr. Kaps (Chair), Dr. Gaj, Dr. Mark, and Dr. Simon. (12/02/2017)


Duc Nguyen won 3rd place in the International Students' Olympiad in Cryptography NSUCRYPTO-2017

Duc Nguyen won third place in the International Students' Olympiad in Cryptography, NSUCRYPTO-2017, held on October 22-30, 2017. Duc participated in Round 2 for Professionals as a member of the team, including two of his colleagues from Ho Chi Minh City, Vietnam: Dat Bui Minh Tien and Quan Doan. The results of the competition were announced on December 1, 2017. Duc and his team repeated their 3rd place finish from 2016, but scored a higher percentage of the maximum score, 37 out of 60 (61.7%) in 2017 vs. 27 out of 64 (42.1%) in 2016. (12/01/2017)


GMU Team contributed an improved software implementation to the NIST submission package of the PQC candidate DAGS

Richard Haeussler and Duc Nguyen contributed an improved software implementation to the submission package of the Post-Quantum Cryptography algorithm DAGS. DAGS is a Key Encapsulation Mechanism (KEM) based on Quasi-Dyadic Generalized Srivastava codes. It's list of co-authors, specification, and software implementations are available at the DAGS project website. DAGS is one of 69 candidates qualified to Round 1 of the NIST PQC Standardization Process. (11/30/2017)


William Diehl gave a presentation at FPL 2017

William Diehl attended the 27th International Conference on Field-Programmable Logic and Applications, FPL 2017, held in Ghent, Belgium, on September 4-8, 2017. As part of this conference, William gave a short talk and presented a poster, entitled "Comparison of Hardware and Software Implementations of Selected Lightweight Block Ciphers," based on the paper co-authored with Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps and Kris Gaj. Additionally, William attended the workshop FPGAs for Software Programmers, FSP 2017, co-located with FPL. (09/08/2017)


Sanjay Deshpande spoke at DSD 2017

Sanjay Deshpande spoke at the Euromicro Conference on Digital System Design, held in Vienna, Austria, on August 30-September 1, 2017. He delivered an oral presentation entitled "Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates," co-authored with Kris Gaj. (09/02/2017)


CERG welcomed new members

At the end of August 2017, CERG welcomed new members: Viet Ba Dang who completed his BS degree in Electronics and Telecommunication at the Danang University of Science and Technology in Vietnam in 2016, Duc Tri Nguyen who completed his B.Eng in Computer Engineering at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Vietnam in 2015, and Chaitanya Neelamraju, who earned his Bachelor of Technology degree in Electronics & Communication Engineering (ECE) from Mahaveer Institute of Science & Technology, JNTUH in India in 2016. Viet and Duc will pursue their PhD degrees, and Chaitanya will work on his Master's thesis, all under the supervision of Dr. Gaj, with the focus on the area of post-quantum cryptography. (09/01/2017)


Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology:

Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Ho Chi Minh City, Vietnam, on Aug. 16, 2017. His presentation was entitled "From AES to Post-Quantum Cryptography: FPGA Battles of Cryptographic Algorithms". It was attended by more than 30 faculty members and students from the Faculty of Computer Science and Engineering of the Bach Khoa University. (08/17/2017)


Presentation summarizing benchmarking of Round 3 CAESAR Candidates

The GMU Benchmarking Team has published and announced a comprehensive presentation, entitled "Benchmarking of Round 3 CAESAR Candidates in Hardware: Methodology, Designs & Results," made available at the CAESAR page of the ATHENa website. The GMU Team has contributed high-speed RTL implementations of AES-GCM and 11 Round 3 CAESAR Candidates. (08/11/2016)


Ahmad Salman defended his PhD Thesis

Ahmad Salman defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Kaps (Chair), Dr. Gaj , Dr. Homayoun , and Dr. Stavrou. In the middle of August 2017, Ahmad joined James Madison University in Harrisonburg, VA, as a tenure-track Assistant Professor. (2017/08/15)


Malik Umar Sharif defended his PhD Thesis

Malik Umar Sharif defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun , and Dr. Simon. Since March 2017, Umar has been already working as an FPGA Engineer at ixia, near Portland, OR. (2017/08/15)


Rabia Shahid defended her PhD Thesis

Rabia Shahid defended her PhD Thesis, entitled "A New Approach to the Development of Coprocessors for Pairing-based Cryptosystems," on July 31, 2017. The members of her dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun, and Dr. Albanese. In mid-August 2017, Rabia joined ixia, near Portland, OR, as an FPGA Engineer. (2017/08/15)


Dr. Gaj and Dr. Kaps attended PQCrypto 2017

Dr. Gaj and Dr. Kaps attended the 8th International Conference on Post-Quantum Cryptography, PQCrypto 2017, held in Utrecht, the Netherlands, June 26-28, 2017. During the Recent Result Session on June 26, chaired by Dr. Wouter Castryck, Dr. Gaj delivered a short presentation entitled "High-Speed Hardware for NTRUEncrypt-SVES: Lessons Learned", co-authored with Malik Umar Sharif. Additionally, Dr. Kaps attended a week-long Summer School on Post-Quantum Cryptography (organized by the H2020 project PQCRYPTO), and Dr. Gaj attended a two-day Executive School on Post-Quantum Cryptography (organized by the H2020 project ECRYPT-CSA). Both schools were held at the Technische Universiteit Eindhoven on June 19-23 and June 22-23, 2017, respectively. (06/29/2017)


Dr. Gaj spoke at CryptArchi 2017

Dr. Gaj spoke at the 15th International Workshop on Cryptographic Architectures Embedded in Logic Devices, CryptArchi 2017, held in Smolenice, Slovakia, on June 18-21, 2017. He delivered a talk entitled "Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems," co-authored with Malik Umar Sharif and Ahmed Ferozpuri. (06/22/2017)


Dr. Gaj spoke at the Workshop on Hardware Benchmarking 2017

Dr. Gaj spoke at the Workshop on Hardware Benchmarking, held in Bochum, Germany, on June 7, 2017. He delivered an invited talk entitled "Fair and Efficient Hardware Benchmarking of Candidates in Cryptographic Contests". (06/07/2017)


Rabia Shahid spoke at RAW 2017

Rabia Shahid spoke at the 24th Reconfigurable Architecture Workshop - RAW 2017, co-located with the 31st Annual IEEE International Parallel and Distributed Processing Symposium - IEEE IPDPS 2017, held in Orlando, Florida, on May 29-June 2, 2017. She delivered a talk entitled "A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems," based on the paper co-authored with Ted Winograd and Dr. Gaj. (06/01/2017)


Farnoud Farahmand earned internship at Google

Farnoud Farahmand has earned the position of the Hardware Engineer Intern at Google in Mountain View, CA, held between May 30 and August 25, 2017. (05/30/2017)


Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards

CERG Members, Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards, handed to them by the ECE Department Chair, Prof. Monson Hayes, during the ECE Convocation Reception on May 18, 2017. Here is a photo of all awardees together with their academic advisor Dr. Gaj. (05/19/2017)


William Diehl qualified to the finals of the 3M Thesis Competition

William Diehl qualified to the finals of the 3-Minute Thesis competition. The preliminary round was held on March 3, 2017, in the HUB Rooms 4 & 5. 48 GMU doctoral students entered the contest, of whom 20 were from the Volgenau School of Engineering. Each contestant had three minutes (and one Powerpoint slide) to explain his/her research to a general audience. William was the only student representing CERG. The finals were held on Saturday, March 25, at Mason's Arlington Campus. They were part of the Mason Graduate Interdisciplinary Conference. An article about the competition, with a quote from William, was written by Martha Bushong, and published in News at Mason. The full video of his talk is available here. (03/06/2017)


Dr. Gaj's research featured in the Spring 2017 ECE Newsletter

Dr. Gaj's research has been featured in the Spring 2017 ECE Newsletter. The article about Dr. Gaj is called "Battles for Cryptographic Algorithms". (02/11/2017).


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, The CAESAR-api in the real world - towards a fair evaluation of hardware CAESAR candidates, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Side-channel resistant soft core processor for lightweight block ciphers, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • F. Farahmand, A. Ferozpuri, W. Diehl, and K. Gaj, Minerva: Automated hardware optimization tool, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, IEEE, Dec., 2017 [Bibtex]
  • P. Yalla and J.-P. Kaps, Evaluation of CAESAR hardware API for lightweight implementations, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • A. Salman, W. Diehl, and J.-P. Kaps, A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • E. Homsirikamol and K. Gaj, Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, Dec, 2017 [Bibtex]
  • B. Jarvis and K. Gaj, Selection of an error-correcting code for FPGA-based Physical Unclonable Functions, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, IEEE, Dec., 2017 [Bibtex]
  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • S. Deshpande and K. Gaj, Analysis and inner-round pipelined implementation of selected parallelizable CAESAR competition candidates, 19th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, Aug., 2017 [Bibtex]
  • B. Habib, J.-P. Kaps, and K. Gaj, Implementation of efficient SR-latch PUF on FPGA and SoC devices, Microprocessors and Microsystems, volume 53, pages 92-105, Aug., 2017 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of selected CAESAR round two authenticated ciphers, Microprocessors and Microsystems, volume 52, pages 202-218, July, 2017 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Microprocessors and Microsystems, volume 51, pages 239-251, June, 2017 [Bibtex]
  • R. Shahid, T. Winograd, and K. Gaj, A generic approach to the development of coprocessors for Elliptic Curve Cryptosystems, 24th Reconfigurable Architectures Workshop, RAW 2017, Orlando, FL, May, 2017 [Bibtex]
  • C. Marchand, L. Bossuet, and K. Gaj, Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes, International Journal of Circuit Theory and Applications, volume 45, pages 274-291, Feb., 2017 [Bibtex]
  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]