CERG Support of CAESAR


CERG is deeply involved in CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness. Members of CERG have developed the CAESAR Hardware API for authenticated ciphers, approved by the CAESAR Committee. Our group has also developed comprehensive Development Package, including VHDL and Python code common for all candidates, and the corresponding Implementer's Guide. CERG has contributed optimized high-speed RTL implementations for 24 Round 2 CAESAR Candidates and AES-GCM. Members of our team have also conducted comprehensive FPGA benchmarking of all Round 2 implementations, submitted by 14 hardware design teams from all over the world. The comprehensive rankings can be reviewed by accessing the ATHENa Database of Results. The summary of the Round 2 RTL benchmarking effort and an alternative benchmarking methodology based on High-Level Synthesis were presented at DIAC 2016. Additionally, two current members (Ice and Dr. Gaj) and one former member of CERG (Marcin) were co-authors of ICEPOLE, a high-speed, hardware-oriented Round 2 CAESAR candidate, suitable for any environment where specialized hardware (such as FPGAs or ASICs) could be used to provide high data processing rates.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


A Scalable ECC Processor for High-Speed and Light-Weight Implementations with Side-Channel Countermeasure

Ahmad Salman, ECE PhD Seminar
Date: Friday, June 16th, 3:00 PM - 4:00 PM
Location: Engineering Building, Room 3203

With the growing number of devices connected to the Internet, the need for flexible Public Key Cryptosystems (PKC) that can be supported by multiple platforms while maintaining a high level of security is essential. The performance of PKC based on elliptic curves is mostly dependent on the performance of the underlying field arithmetic. In this work, we present high-speed and lightweight implementations of a fully scalable architecture of an Elliptic Curve Cryptography (ECC) scalar multiplier processor. The processor supports operations over GF(p) for arbitrary values of p, and field sizes up to 521 bits. The implementations perform modular multiplication operations using fully scalable Montgomery multiplier architectures, one tailored for high-speed and one for lightweight. Point addition and point doubling operations are performed over Co-Z projective coordinates. While transmission and storage are done in affine coordinates. In addition to having dedicated high-speed and lightweight architectures, both also support different bus widths to increase flexibility and allow for a wide range of applications. Our cores include countermeasures to side-channel attacks by using the Montgomery Ladder and Exponent Randomization methods to provide resistance to Simple Power Analysis (SPA) and Differential Power Analysis (DPA) respectively.

We have implemented the design on FPGA and All Programmable System on Chip platforms from different vendors as well as using a standard-cell ASIC library in order to provide comprehensive results We also analyzed power and energy consumptions for each implemented design to determine the relation between area/throughput trade-off and power and energy consumptions. We have evaluated our designs based on NIST recommended field lengths - 192, 224, 256, 384 and 521 bits - using several arbitrary values of prime p

Latest News:

Dr. Gaj will speak at the Workshop on Hardware Benchmarking 2017

Dr. Gaj will speak at the Workshop on Hardware Benchmarking, held in Bochum, Germany, on June 7, 2017. He will deliver an invited talk entitled "Fair and Efficient Hardware Benchmarking of Candidates in Cryptographic Contests". (06/07/2017)

Rabia Shahid spoke at RAW 2017

Rabia Shahid spoke at the 24th Reconfigurable Architecture Workshop - RAW 2017, co-located with the 31st Annual IEEE International Parallel and Distributed Processing Symposium - IEEE IPDPS 2017, held in Orlando, Florida, on May 29-June 2, 2017. She delivered a talk entitled "A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems," based on the paper co-authored with Ted Winograd and Dr. Gaj. (04/08/2017)

William Diehl qualified to the finals of the 3M Thesis Competition

William Diehl qualified to the finals of the 3-Minute Thesis competition. The preliminary round was held on March 3, 2017, in the HUB Rooms 4 & 5. 48 GMU doctoral students entered the contest, of whom 20 were from the Volgenau School of Engineering. Each contestant had three minutes (and one Powerpoint slide) to explain his/her research to a general audience. William was the only student representing CERG. The finals were held on Saturday, March 25, at Mason's Arlington Campus. They were part of the Mason Graduate Interdisciplinary Conference. An article about the competition, with a quote from William, was written by Martha Bushong, and published in News at Mason. (03/06/2017)

Dr. Gaj's research featured in the Spring 2017 ECE Newsletter

Dr. Gaj's research has been featured in the Spring 2017 ECE Newsletter. The article about Dr. Gaj is called "Battles for Cryptographic Algorithms". (02/11/2017).

Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]