Database of FPGA Results for Authenticated CiphersShow Help
All results are categorized in groups, e.g., Algorithm, Design , Platform, etc. Clicking on the group name reveals additional columns for the respective group. Clicking on the group name again collapses the group.
Each column has a column title e.g. Result ID, Primary Opt. Target, TP [Mbits/s] (meaning Throughput) etc. Clicking on the column title sorts the column in ascending order, clicking on it again sorts it in descending order. In addition, the little arrow next to the title changes color to indicate the sort order and the column is shaded. A second order of sorting can be achieved by pressing the "Shift" key on the keyboard and then clicking on another column title.
At the bottom of each column is a search box. Any entry in these boxes is only applied to the respective column. The search is not case sensitive, and is regex based. An OR operation can be accomplished by surrounding search terms w/ parenthesis and seperating them with a pipe, like so:
(term1|term2)The number of results matching the current search criteria is shown at the end of the table, below the paging buttons.
Clicking on a Result ID opens a page that shows all details about that particular result.
To compare two results, click one result, then another to compare against. Then click the 'Compare Selected Results' action
In order to preserve the state of the table when examining a result, please right-click and select "open in new window" or "open in new tab". Alternatively, use middle click on a result id.
Numeric and date columns may be searched using by specifying a range in ISO interval notation, or a simple one sided bound using >. For example, to search for all results with values between 1000 and 2000, inclusive, use:
[1000,2000]To search for values greater than 2000 exclusive, use:
> 2000Date ranges may also be entered using a date picker, activated by clicking "Enter Date Range" below the appropriate field.
The "Enable Unique" link in the algorithms columns limits results to one per algorithm.
|Result ID||group||Algorithm||Key Size [bits]||Assoc Data||Secret Message #||Secret Message # Size [bits]||Msg Blk Size [bits]||Design ID||Impl Approach||Hardware API||ceil(log2(Max Len))||Primary Opt Target||Secondary Opt Target||Arch Type||Language||Megafunctions or Primitives||Max #Streams||Clk Cycles per Block (Long Msg)||Datapath Width [bits]||Padding||Input Bus Width [bits]||Key Sched Time Formula||Enc/Auth Time Formula||Dec/Auth Time Formula||Auth-Only Time Formula||Interface/Protocol Spec||Src Avail||Device Vendor||Family||LUTs||CLB Slices||ALUTs||LEs||ALMs||Flip Flops||MULTs||DSPs||BRAMs||Memory Bits||Impl Freq [MHz]||Enc/Auth TP [Mbits/s]||Dec/Auth TP [Mbits/s]||Auth-Only TP [Mbits/s]||Synth Freq [MHz]||Key Sched Time [ns]||(Enc/Auth TP)/Slice [(Mbits/s)/Slice]||(Enc/Auth TP)/LUT [(Mbits/s)/LUT]||(Dec/Auth TP)/Slice [(Mbits/s)/Slice]||(Dec/Auth TP)/LUT [(Mbits/s)/LUT]||(Auth-Only TP)/LUT [(Mbits/s)/LUT]||(Auth-Only TP)/Slice [(Mbits/s)/Slice]||(Enc/Auth TP)/LE [(Mbits/s)/LE]||(Dec/Auth TP)/LE [(Mbits/s)/LE]||(Auth-Only TP)/LE [(Mbits/s)/LE]||(Enc/Auth TP)/ALUT [(Mbits/s)/ALUT]||(Enc/Auth TP)/ALM [(Mbits/s)/ALM]||(Dec/Auth TP)/ALM [(Mbits/s)/ALM]||(Dec/Auth TP)/ALUT [(Mbits/s)/ALUT]||(Auth-Only TP)/ALM [(Mbits/s)/ALM]||(Auth-Only TP)/ALUT [(Mbits/s)/ALUT]||Estimated Power [mW]||Estimated Energy/Bit [mJ/Gbit]||Measured Power [mW]||Measured Energy/Bit [mJ/Gbit]||HLS Tool||HLS Tool Input Lang||HLS Tool Output Lang||HLS Tool Version||HLS Tool Options||Synth Tool||Synth Tool Version||Impl Tool||Impl Tool Ver||Primary Designer Name(s)||Primary Designer Affiliation||Result Modify Date||Design Entered By|