GMU Source Code

    Algorithm Best Non-Pipelined High-Speed Architecture Architecture Notation
    Release Date
    BLAKE /2(h)
    x1 (P+Q)
    x1 (P/Q)
    JH x1
    Keccak x1
    Skein x4
    SHA-2 x1
  • Folded & Unrolled Architectures without padding

  • Algorithm Folded & Unrolled Architectures
    Architecture Notations
    Release Date
    x1, /k(h);       k=2,4
    /k(v) (P+Q);   k=2,4,8
    /k(v) (P/Q);    k=2,4,8
    Skein xk;                 k=1,4,8
  • Block Diagrams for the SHA-3 Round 3 Candidates - Basic, Folded, and Unrolled Architectures

  • Algorithm Block Diagrams
    Release Date
    BLAKE 10/08/2011
    Groestl 10/10/2011
    JH 10/08/2011
    Keccak 10/01/2011
    Skein 10/08/2011

  • Source Code for the SHA-3 Round 2 Candidates & SHA-2 - Hash 2011 Release, May 2011

  • Assumptions:

    1. Primary Optimization Target:   Throughput/Area;   Secondary Optimization Target:   Throughput.
    2. Datapath width = Internal state size.
    3. The GMU Interface and Communication Protocol Used in the Implementations the SHA-3 Round 2 Candidates.
    4. No padding unit  (i.e., input is assumed to be already properly padded).
    5. No salt, No special modes of operation.
    6. No use of embedded resources, such as multipliers, DSP units, or Block Memories.
    7. The VHDL file containing the top level entity of the given hash function is indicated in the source_list.txt file present in the 'sources' folder obtained from the zip file. The only exception to this rule is SIMD, in which VHDL code for 256 and 512-bit variants are in separate folders inside the zip file.

    Algorithm Basic High-Speed Architecture Release Date
    BLAKE 05/19/2011
    BMW 05/19/2011
    CubeHash 05/19/2011
    ECHO 05/19/2011
    Fugue 05/19/2011
    Groestl 08/31/2011
    Hamsi 05/19/2011
    JH 05/19/2011
    Keccak 05/19/2011
    Luffa 05/19/2011
    Shabal 05/19/2011
    SHAvite-3 05/19/2011
    SIMD 05/19/2011
    Skein 05/19/2011
    SHA-2 05/19/2011


  • Implementation Results

  • The results for all of the above listed implementations are available in the ATHENa database. In order to get familiar with the database please start from reading its help.
    For each Round 3 source code, an effort has been made to generate results for the following 4 families of FPGAs:
    • Altera Stratix III, and Stratix IV, and 
    • Xilinx Virtex 5, and Virtex 6. 
    For each Round 2 source code, an effort has been made to generate results for the following 11 families of FPGAs:
    • Altera Cyclone II, Cyclone III, Cyclone IV, Stratix II, Stratix III, and Stratix IV, and 
    • Xilinx Spartan 3, Spartan 6, Virtex 4, Virtex 5, and Virtex 6. 
    Please note that for some large designs, it might have been impossible to implement them using certain low-cost families.
    You can use filters at the bottom of the Hash Function Results Table in the database in order to limit your view to implementations of a particular algorithm, using particular family. In order to distinguish between the Round 2 and Round 3 versions of the same algorithm, please click on the header Algorithm, and then specify in the filter for the Group, SHA-3 Round 2 or SHA-3 Round 3, respectively.
    In order to investigate any particular result in detail, please click on its ID. An overlay window should appear. In order to compare two results, please choose one result (by clicking anywhere within a line corresponding to this result), and then choose another one you would like to use for comparison. Then click on the "Compare Selected Results" button.
  • Replicating GMU Results

  • In order replicate a selected result available in the ATHENa database, you need to
    1. Locate the result in the ATHENa database, using available filters and search functions.
    2. Click on the result ID in the left-most column.
    3. Scroll to the bottom of the overlay window, to the category Other, and the field: Result Replication Files:  link.
    4. Right-click on the string "link" and download the associated file <Result ID>.zip to a selected folder of your choice.
    5. Unzip the obtained file. Get familiar with the readme.txt file located in the main folder after decompression.
    6. Copy source code used to generate a given result, downloaded from this web page, to the folder src of the replication folder.
    7. Run the replication script, called 'run', to re-generate the result. In Windows, this can be done either by double-clicking on "run.bat", or calling this script from the command-line window. In Linux, the user may need to change the ownership of "" first, by calling "chmod +x" in the console window. Afterwards, the user should call the "./" command.
    8. Check implementation reports generated by the FPGA tools, these reports are generated as *.log and *.twr files and are located inside the replication folder. 
  • Checking Functional Correctness of the Code

  • All source code zip files from GMU contain the following subfolders:
    • kat       : Known Answer Test folder containing test vectors used to test our designs.
    • sources   : Source files folder.
    • tb        : Testbench files folder.

    To perform functional simulation, you need to:
    1. Add all the source files from the 'sources' folder
    2. Add all the testbench files from the 'tb' folder
    3. Copy the KAT files from the 'kat' folder to your verification tool's project folder
    4. Compile the files with the following hierarchy (top last):
      1. synthesizable source files in the same order as in source_list.txt file
      2. sha_tb_all_pkg.vhd
      3. fifo_ram.vhd
      4. fifo.vhd
      5. hash_one_clk_wrapper or hash_two_clk_wrapper (whichever file is present in the tb folder)
      6. sha_tb_all.vhd.
    5. Perform functional verification with sha_tb_all as your top level entity.
  • Source Code from Other Groups

  • SHA-3 Round 3 and Round 2 Candidates: SHA-3 Round 2 Candidates:
  • Contact information

  • Please contact us with any ideas about the desired features of our code, error reports, questions, etc.

    Please indicate if you would like to receive e-mail notifications about the releases of new versions of our source code.

    Please direct your correspondence to:

    Kris Gaj
    CERG: Cryptographic Engineering Research Group
    ECE Department
    George Mason University
    Fairfax, VA 22030

    E-mail: kgaj (at)
    Phone:  +1 703 993 1575
    Fax:      +1 703 993 1601

    You can also contact directly the primary author of a particular code (typically a graduate student), using name and an e-mail address provided in the fields Primary Designer Name(s) and Primary Designer Email(s) in the detailed view of any result obtained using that particular code.