History of Updates
v1.3 : June 16, 2016
- Added the generic G_SBOX_LOGIC to all top-level AES units: AES_Enc, AES_Enc_KOF, and AES_EncDec.
If G_SBOX_LOGIC = False (default), each AES S-box is implemented using a 256 x 8 ROM.
If G_SBOX_LOGIC = True, then each AES S-box is implemented using logic only,
according to the method described in Section 10.6.1.3 Logic Only of
K. Gaj and P. Chodowiec, "
FPGA and ASIC Implementations of AES," Chapter 10
in C.K. Koc (Ed.), Cryptographic Engineering, pp. 235-320, Springer, Dec. 2008
(based on D. Canright, "
A very compact S-box for AES," Proc. CHES 2005.)
- Added the generic G_OBUF to all top-level AES units: AES_Enc, AES_Enc_KOF, and AES_EncDec.
If G_OBUF = False (default), then there is no register at the output dout of the AES Round,
and processing of each block takes 10 clock cycles.
If G_OBUF = True, then there is an extra register at the output dout of the AES Round.
As a result, processing of each block takes 11 clock cycles, but the minimum
clock period is shorter than in the former case.
v1.2 : November 22, 2014
v1.1 : November 16, 2014
v1.0 : Initial release : November 3, 2014