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2016

  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]

2015

  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, Efficient SR-latch PUF, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 205–216, Apr., 2015 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 217-228, Apr, 2015 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]

2014

  • E. Homsirikamol and K. Gaj, Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study., 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2014, IEEE, pages 1–8, Dec., 2014 [Bibtex]
  • P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wójcik, ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption, Cryptographic Hardware and Embedded Systems, CHES 2014, LNCS, volume 8731, Springer Berlin Heidelberg, pages 392–413, Sep., 2014 [Bibtex]
  • M. Rogawski, E. Homsirikamol, and K. Gaj, A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs, 24th International Conference on Field Programmable Logic and Applications – FPL 2014, IEEE, pages 1–8, Sep., 2014 [Bibtex]

2013

  • B. Habib, K. Gaj, and J.-P. Kaps, FPGA PUF based on programmable LUT delays, 2013 Euromicro Conference on Digital System Design (DSD), pages 697–704, 2013 [accepted version, pdf] [Bibtex]
  • R. Velegalati, K. Shah, and J.-P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, 2013 Euromicro Conference on Digital System Design (DSD), pages 947–954, 2013 [Bibtex]
  • M. Rogawski, K. Gaj, and E. Homsirikamol, A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl, Microprocessors and Microsystems, volume 37, number 6-7, pages 572-582, 2013 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS), June, 2013, Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI 2013 [pdf] [Bibtex]

2012

  • B. Brewster, E. Homsirikamol, R. Velegalati, and K. Gaj, Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules, 2012 International Conference on Field Programmable Technology - FPT, Dec, 2012 [Bibtex]
  • S. Paul, E. Homsirikamol, and K. Gaj, A Novel Permutation-based Hash Mode of Operation FP and The Hash Function SAMOSA, 13th International Conference on Cryptology in India - Indocrypt, Dec, 2012 [Bibtex]
  • M. Rogawski and K. Gaj, A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grostl, 15th EUROMICRO Conference on Digital System Design – DSD 12, 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Jun., 2012 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis, May, 2012, Work in Progress (WiP), Third International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2012 [pdf] [Bibtex]
  • C. Wenzel-Benner, J. Gr"af, J. Pham, and J.-P. Kaps, XBX benchmarking results January 2012, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex] Third {SHA-3} candidate conference
  • F.K. G"urkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference

2011

  • R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [pre-print, pdf] [Bibtex]
  • A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig`11, IEEE, pages 242–248, Dec, 2011 [pre-print, pdf] [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Throughput vs. Area trade-offs architectures of five Round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs, Workshop on Cryptographic Hardware and Embedded Systems CHES 2011, LNCS, volume 6917, Springer Berlin / Heidelberg, pages 491–506, Sep, 2011 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [pre-print, pdf] [Bibtex]
  • X. Xin, J.-P. Kaps, and K. Gaj, A configurable ring-oscillator-based PUF for Xilinx FPGAs, 14th EUROMICRO Conference on Digital System Design – DSD'11, IEEE, pages 651–657, Aug, 2011 [pre-print, pdf] [Bibtex] Nominated for Best Paper Award
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]

2010

  • S. Shah, R. Velegalati, J.-P. Kaps, and D. Hwang, Investigation of DPA resistance of Block RAMs in cryptographic implementations on FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'10, IEEE, pages 274–279, Dec, 2010 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic, International Conference on Electronics, Circuits, and Systems, ICECS 2010, IEEE, pages 1251–1254, Dec, 2010 [pre-print, pdf] [Bibtex]
  • K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, and B.Y. Brewster, ATHENa – automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs, 20th International Conference on Field Programmable Logic and Applications - FPL 2010, IEEE, pages 414–421, 2010 [accepted version, pdf] [Bibtex] Winner of the FPL Community Award.
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs, 2010, Cryptology ePrint Archive, Report 2010/445 [link] [Bibtex]
  • K. Gaj, E. Homsirikamol, and M. Rogawski, Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGA, Cryptographic Hardware and Embedded Systems, CHES 2010, LNCS, volume 6225, Springer Berlin / Heidelberg, pages 264–278, 2010 [Bibtex]
  • J.-P. Kaps and R. Velegalati, DPA resistant AES on FPGA using partial DDL, IEEE Symposium on Field-Programmable Custom Computing Machines – FCCM 2010, IEEE, pages 273–280, May, 2010 [pre-print, pdf] [Bibtex]

2009

  • P. Yalla and J.-P. Kaps, Lightweight cryptography for FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'09, IEEE, pages 225–230, Dec., 2009 [pre-print, pdf] [Bibtex]
  • Cryptographic hardware and embedded systems – CHES 2009, Lecture Notes in Computer Science , volume 5747 , Springer, Sep., 2009 [Bibtex] Christophe Clavier and Kris Gaj, editors.
  • C. Shu, S. Kwon, and K. Gaj, Reconfigurable computing approach for tate pairing cryptosystems over binary fields, IEEE Transactions on Computers, volume 58, pages 1221-1237, Sep., 2009 [Bibtex]
  • K. Gaj and P. Chodowiec, Cryptographic engineering, Springer, FPGA and ASIC Implementations of AES, pages 235–294, 2009 [Bibtex]
  • R. Velegalati and J.-P. Kaps, DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 385–390, Aug, 2009 [, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Compact FPGA implementation of Camellia, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 658–661, Aug., 2009 [pre-print, pdf] [Bibtex]

2008

  • J.-P. Kaps, Chai-tea, cryptographic hardware implementations of xTEA, Progress in Cryptology – INDOCRYPT 2008, Lecture Notes in Computer Science (LNCS), volume 5365, Springer, Heidelberg, pages 363–375, Dec, 2008 [extended version, pdf] [Bibtex]
  • R. Vaslin, G. Gogniat, J.-P. Diguet, R. Tessier, and K. Gaj, Memory security management for reconfigurable embedded systems, Proc. International Conference on Field Programmable Technology, FPT 2008, Taipei, pages 153–160, Dec, 2008 [Bibtex]
  • P. Saha, E. El-Araby, M. Huang, M. Taher, S. Lopez-Buedo, T. El-Ghazawi, C. Shu, K. Gaj, A. Michalski, and D. Buell, Portable library development for reconfigurable computing systems: A case study, Elsevier Parallel Computing: Systems & Applications, volume 34, number 4+5, pages 245–260, May, 2008 [Bibtex]
  • P. Schaumont and D. Hwang, Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits, IEEE International Symposium on Circuits and Systems (ISCAS), pages 3178-3181, May, 2008 [Bibtex]
  • T. El-Ghazawi, E. El-Araby, M. Huang, K. Gaj, V. Kindratenko, and D. Buell, The promise of high-performance reconfigurable computing, Computer, volume 41, number 2, pages 69-76, Feb, 2008 [Bibtex]
  • D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj, Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates, State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pages 151–162, Feb, 2008 [pdf] [Bibtex]
  • M. Huang, K. Gaj, S. Kwon, and T. El-Ghazawi, An optimized hardware architecture for the Montgomery Multiplication Algorithm, PKC 2008: 11th International Workshop on Practice and Theory in Public Key Cryptography, Barcelona, Spain, pages 214-228, March, 2008 [pdf] [Bibtex]

2007

  • G. Southern, C. Mason, L. Chikkam, P. Baier, and K. Gaj, FPGA implementation of high throughput circuit for trial division by small primes, SHARCS 2007: Special-purpose Hardware for Attacking Cryptographic Systems, SHARCS, pages 3-21, Sep, 2007 [pdf] [Bibtex]
  • A. Abusharekh and K. Gaj, Comparative analysis of software libraries for public key cryptography, Software Performance Enhancement for Encryption and Decryption, SPEED 2007, Amsterdam, the Netherlands, pages 3–19, June, 2007 [pdf] [Bibtex]
  • D. Buell, T. El-Ghazawi, K. Gaj, and V. Kindratenko, High-performance reconfigurable computing: Guest editors' introduction, IEEE Computer, volume 40, number 3, pages 23–27, Mar, 2007 [pdf] [Bibtex]
  • J.-P. Kaps, G. Gaubatz, and B. Sunar, Cryptography on a speck of dust, Computer, volume 40, number 2, pages 38–44, Feb, 2007 [Pre-print, pdf] [Bibtex]
  • K. Gaj, G. Southern, and R. Bachimanchi, Comparison of hardware performance of selected phase 2 eSTREAM candidates, State of the Art of Stream Ciphers, SASC 2007, Bochum, Germany, Jan-Feb, 2007 [pdf] [Bibtex]

2006

  • K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M. Khaleeluddin, and R. Bachimanchi, Implementing the elliptic curve method of factoring in reconfigurable hardware, Cryptographic Hardware and Embedded Systems – CHES 2006, Lecture Notes in Computer Science (LNCS), volume 4249, Springer , Berlin / Heidelberg, pages 119–133, Oct, 2006 [php] [Bibtex]
  • J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing, Embedded and Ubiquitous Computing (EUC-06) Workshop Proceedings, Lecture Notes in Computer Science (LNCS), volume 4097, Springer, pages 372–381, Aug, 2006 [expanded version, pdf] [Bibtex]
  • J.-P. Kaps, Cryptography for ultra-low power devices, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 2006, Ph.D. Dissertation [pdf] [Bibtex]
  • I. Verbauwhede, K. Tiri, D. Hwang, and P. Schaumont, Circuits and design techniques for secure ICs resistant to side-channel attacks, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT '06), May, 2006 [Bibtex]
  • D. Hwang, K. Tiri, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks, IEEE Journal of Solid-State Circuits, volume 41, number 4, pages 781–792, Apr, 2006 [Bibtex]
  • D. Hwang, P. Schaumont, K. Tiri, and I. Verbauwhede, Securing embedded systems, IEEE Security & Privacy Magazine, volume 4, number 2, pages 40-49, Mar, 2006 [Bibtex]
  • D. Misra and K. Gaj, Face recognition CAPTCHAs, AICT-ICIW '06: Proceedings of the Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services, IEEE Computer Society, Washington, DC, USA, 2006 [Bibtex]

2005

  • J.-P. Kaps, K. Yüksel, and B. Sunar, Energy scalable universal hashing, IEEE Transactions on Computers, volume 54, number 12, pages 1484–1495, Dec, 2005 [pdf] [Bibtex]
  • C. Zouridaki, M. Hejmo, B. Mark, R. Thomas, and K. Gaj, Analyis of attacks and defense mechanisms of QoS signaling, WIS 2005, may, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, E. Öztürk, and B. Sunar, State of the art in ultra-low power public key cryptography for wireless sensor networks, Third IEEE International Conference on Pervasive Computing and Communications Workshops, Workshop on Pervasive Computing and Communications Security–PerSec'05, IEEE Computer Society, pages 146–150, Mar, 2005 [pdf] [Bibtex]
  • K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, A side-channel leakage free coprocessor IC in 0.18μm CMOS for embedded AES-based cryptographic and biometric processing, 42nd Design Automation Conference, pages 222–227, 2005 [Bibtex]
  • K. Tiri, D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, Prototype IC with WDDL and differential routing – DPA resistance assessment, Cryptographic Hardware and Embedded Systems – CHES 2005, Lecture Notes in Computer Science (LNCS), volume 3659, Springer, pages 354–365, 2005 [Bibtex]

2004

  • G. Gaubatz, J.-P. Kaps, and B. Sunar, Public key cryptography in sensor networks—revisited, 1st European Workshop on Security in Ad-Hoc and Sensor Networks (ESAS 2004), Lecture Notes in Computer Science (LNCS), volume 3313, Springer, Heidelberg, pages 2–18, August, 2004 [pdf] [Bibtex]
  • S. Bajracharya, C. Shu, K. Gaj, and T. El-Ghazawi, Implementation of elliptic curve cryptosystems over GF(2^n) in optimal normal basis on a reconfigurable computer, 14th International Conference on Field Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, pages 1001-1005, Aug, 2004 [pdf] [Bibtex]
  • K. Yüksel, J.-P. Kaps, and B. Sunar, Universal hash functions for emerging ultra-low-power networks, Proceeding of The Communications Networks and Distributed Systems Modeling and Simulation Conference (CNDS), Society for Modeling and Simulation International (SCS), San Diego, CA, January, 2004 [pdf] [Bibtex]
  • R. Lien, T. Grembowski, and K. Gaj, A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512, RSA Conference, Cryptographer's Track, CT-RSA 2004, San Francisco, CA, LNCS, volume 2964, pages 324–328, Feb., 2004 [pdf] [Bibtex]

2003

  • K. Gaj, T. El-Ghazawi, N. Alexandridis, J.R. Radzikowski, M. Taher, and F. Vroman, Effective utilization and reconfiguration of distributed hardware using job management systems, Reconfigurable Architecture Workshop, RAW 2003, April, 2003 [pdf] [Bibtex]
  • O. Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, and N. Alexandridis, Performance and overhead in a hybrid reconfigurable computer, Reconfigurable Architecture Workshop, RAW 2003, April, 2003 [pdf] [Bibtex]

2002

  • K. Gaj, T. El-Ghazawi, N. Alexandridis, F. Vroman, N. Nguyen, J. Radzikowski, P. Samipagdi, and S. Suboh, Performance evaluation of selected job management systems, Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems, PMEO 2002, April, 2002 [pdf] [Bibtex]
  • T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, J. Flidr, T. Lehman, and B. Schott, Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512, Information Security, 5th International Conference, ISC 2002, Lecture Notes in Computer Science (LNCS), volume 2433, Springer-Verlag, pages 75–89, 2002 [pdf] [Bibtex]

2001

  • A. Staicu, J. Radzikowski, K. Gaj, N. Alexandridis, and T. El-Ghazawi, Implementation trade-offs of triple DES in the SRC-6e reconfigurable computing environment, Proc. 2001 MAPLD International Conference, Sep., 2001 [pdf] [Bibtex]
  • M. Taher, K. Gaj, T. El-Ghazawi, and N. Alexandridis, Job management system extension to support SLAAC-1v reconfigurable hardware, Proc. 2001 MAPLD International Conference, Sep., 2001 [pdf] [Bibtex]
  • K. Gaj and P. Chodowiec, Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays, LNCS 2020, Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA Conference 2001 - Cryptographers' Track, pages 84-99, Apr., 2001 [pdf] [Bibtex]
  • P. Chodowiec, K. Gaj, P. Bellows, and B. Schott, Experimental testing of the Gigabit IPSec-compliant implementations of Rijndael and Triple DES using SLAAC-1V FPGA accelerator board, 4th International Information Security Conference, ISC 2001, Malaga, Spain, LNCS, volume 2200, pages 220–234, Oct., 2001 [pdf] [Bibtex]

2000

  • K. Gaj and P. Chodowiec, Comparison of the hardware performance of the AES candidates using reconfigurable hardware, Proc. 3rd Advanced Encryption Standard Conference, pages pp. 40-54, April, 2000 [pdf] [Bibtex]

1999

  • J.-P. Kaps and C. Paar, DES auf FPGAs – Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware, Datenschutz und Datensicherheit, volume 23, number 10, Oct, 1999 [pdf] [Bibtex]
  • J.-P. Kaps and C. Paar, Fast DES implementations for FPGAs and its application to a universal key-search machine, Selected Areas in Cryptography, 5th Annual International Workshop, SAC'98, Proceedings, Lecture Notes in Computer Science (LNCS), volume 1556, Queen's University, Kingston, Ontario, Canada, Springer-Verlag, Berlin, pages 234–247, 1999 [, pdf] [Bibtex]

1998

  • J.-P. Kaps, High speed FPGA architectures for the data encryption standard, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 1998, Master's Thesis [, pdf] [Bibtex]