CERG Seminars are held in the Engineering Building on the GMU Fairfax campus unless noted otherwise. Parking is available in the Sandy Creek parking deck near the Engineering Building. Directions to the campus can be found here. The seminar talks are usually 45 to 60 minutes long and are open to the public. If you wish to be notified about future seminars, please send an e-mail to Jens-Peter Kaps.

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A Scalable ECC Processor for High-Speed and Light-Weight Implementations with Side-Channel Countermeasure

Ahmad Salman, ECE PhD Seminar
Date: Friday, June 16th, 3:00 PM - 4:00 PM
Location: Engineering Building, Room 3203

With the growing number of devices connected to the Internet, the need for flexible Public Key Cryptosystems (PKC) that can be supported by multiple platforms while maintaining a high level of security is essential. The performance of PKC based on elliptic curves is mostly dependent on the performance of the underlying field arithmetic. In this work, we present high-speed and lightweight implementations of a fully scalable architecture of an Elliptic Curve Cryptography (ECC) scalar multiplier processor. The processor supports operations over GF(p) for arbitrary values of p, and field sizes up to 521 bits. The implementations perform modular multiplication operations using fully scalable Montgomery multiplier architectures, one tailored for high-speed and one for lightweight. Point addition and point doubling operations are performed over Co-Z projective coordinates. While transmission and storage are done in affine coordinates. In addition to having dedicated high-speed and lightweight architectures, both also support different bus widths to increase flexibility and allow for a wide range of applications. Our cores include countermeasures to side-channel attacks by using the Montgomery Ladder and Exponent Randomization methods to provide resistance to Simple Power Analysis (SPA) and Differential Power Analysis (DPA) respectively.

We have implemented the design on FPGA and All Programmable System on Chip platforms from different vendors as well as using a standard-cell ASIC library in order to provide comprehensive results We also analyzed power and energy consumptions for each implemented design to determine the relation between area/throughput trade-off and power and energy consumptions. We have evaluated our designs based on NIST recommended field lengths - 192, 224, 256, 384 and 521 bits - using several arbitrary values of prime p

Crypto Evening

ECE 746 Advanced Cryptography, Project Presentations
Date: Tuesday, May 1st, 4:30 PM - 8:00 PM
Location: Engineering Building, Room 3507

Join us for an evening of exciting presentations by ECE 746 students. The exact schedule is posted here. Farnoud Farahmand, Abubakr Abdulgadir, and Brian Jarvis of our research group will be presenting. Please come over to cheer them on!