This is the archive of news previously and currently shown on our main page. Seminars are posted on the seminar page. Our latest publications are posted on the publications page.

[Current] [2016] [2015] [2014] [2013] [2012] [2011] [2010] [2009] [2008]


2018

CERG Team will give two demos and one poster presentation at HOST 2018

CERG Team, including Abubakr Abdulgadir, William Diehl, Raghurama Velagala, Dr. Kaps, and Dr. Gaj, will attend the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, to be held in McLean, VA, on April 30-May 4, 2018. During this conference, our team will give two demos entitled: Flexible, Opensource workBench fOr Side-channel analysis (FOBOS) and eXtended eXternal Benchmarking eXtension (XXBX). Additionally, William Diehl will give the poster presentation entitled "Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers," co-authored with Abubakr Abdulgadir, Farnoud Farahmand, Dr. Kaps, and Dr. Gaj. Finally, Michael Tempelmeier from Technical University of Munich (TUM) will give the talk entitled "The CAESAR-API in the Real World - Towards a Fair Evaluation of Hardware CAESAR Candidates," co-authored with Dr. Kaps. (04/20/2018)


CERG Team attended CBC 2018, PQCrypto 2018, and First PQC Standardization Conference

CERG Team, including Viet Dang, Ahmed Ferozpuri, Duc Nguyen, Dr. Gaj, and Dr. Kaps, attended a sequence of the following three conferences: The Sixth Code-Based Cryptography Workshop, CBC 2018, held on April 5-6, 2018; The Ninth International Conference on Post-Quantum Cryptography, PQCrypto 2018, held on April 9-11, 2018, and First PQC Standardization Conference, held on April 11-13, 2018. All conferences were located in Fort Lauderdale, FL. During the CBC 2018 workshop, Viet Dang gave a talk entitled "Hardware Implementation of the Code-based Key Encapsulation Mechanism using Dyadic GS Codes (DAGS)," co-authored with Dr. Gaj. During the Recent Results Session at the PQCrypto 2018 conference, Dr. Gaj, Ahmed Ferozpuri, and Viet Dang gave three short talks entitled, respectively, "PQC Hardware API & Fair Benchmarking of PQC," "High-Speed HW Implementation of the Multivariate Signature Schemes Unbalanced Oil and Vinegar (UOV), and Rainbow," and "Hardware Implementation of DAGS". (04/14/2018)


2017

William Diehl and Dr. Gaj gave presentations at FPT 2017

William Diehl and Dr. Gaj attended the 2017 International Conference on Field-Programmable Technology, FPT 2017, held in Melbourne, Australia, on December 11-13, 2017. William Diehl gave an oral presentation entitled "Comparing the Cost of Protecting Selected Lightweight Block Ciphers Against Differential Power Analysis in Low-Cost FPGAs," based on the paper co-authored with Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. He also gave a poster presentation, entitled "A Light-Weight Hardware/Software Co-Design for Pairing-Based Cryptography with Low Power and Energy," based on the paper co-authored with Ahmad Salman and Jens-Peter Kaps. Dr. Gaj gave an oral presentation entitled "Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study", based on the paper co-authored with Ekawat Homsirikamol. He also gave a poster presentation entitled "Selection of an Error-Correcting Code for FPGA-based Physical Unclonable Functions," based on the paper co-authored with Brian Jarvis. After the main conference, William Diehl and Dr. Gaj attended the full-day workshop entitled "BAMBU: An open-source framework for research in high-level synthesis," presented by Fabrizio Ferrandi from Politecnico di Milano in Italy and Christian Pilato from Universita della Svizzera italiana (USI) in Switzerland. (12/14/2017)


CERG released HLS-ready C code of Round 3 CAESAR candidates

On December 11, 2017, CERG released HLS-ready C code of AES-GCM and 14 Round 3 CAESAR Candidates, targeting Vivado HLS. All implementations have been developed by Ekawat Homsirikamol (a.k.a. Ice) and demonstrated performance comparable with the performance of the corresponding Register-Transfer-Level implementations developed by multiple authors. The release of the code coincided with the presentation of the paper entitled "Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study", co-authored by Ekawat Homsirikamol and Kris Gaj. This project clearly demonstrated that a single designer can develop close-to-optimal implementations of multiple candidates, at the intermediate stages of the cryptographic competitions, and achieve very good correlation between the rankings of candidates implemented using the traditional manual Register-Transfer Level approach and the novel, more efficient High-Level Synthesis approach. (12/11/2017)


William Diehl and Panasayya Yalla gave presentations at ReConFig 2017

William Diehl and Panasayya Yalla attended the 2017 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, held in Cancun, Mexico, on December 4-6, 2017. William Diehl gave an oral presentation entitled "Side-channel Resistant Soft Core Processor for Lightweight Block Ciphers," based on the paper co-authored with Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. gave a poster presentation, entitled "Minerva: Automated Hardware Optimization Tool," based on the paper co-authored with Farnoud Farahmand, Ahmed Ferozpuri, and Kris Gaj. Panasayya Yalla gave an oral presentation entitled "A Scalable ECC Processor Implementation for High-Speed and Lightweight with Side-Channel Countermeasures", based on the paper co-authored with Ahmad Salman, Ahmed Ferozpuri, Ekawat Homsirikamol, Jens-Peter Kaps, and Kris Gaj. He also gave a poster presentation entitled "Evaluation of CAESAR Hardware API for Lightweight Implementations," based on the paper co-authored with Jens-Peter Kaps. (12/07/2017)


Ahmed Ferozpuri defended his Master's Thesis

Ahmed Ferozpuri defended his Master's Thesis entitled "High-Speed Hardware Implementations of Post-Quantum Cryptography Multivariate Signature Schemes," on December 6, 2017. Members of his Committee included: Dr. Gaj (Chair), Dr. Kaps, and Dr. Sasan. (12/07/2017)


CERG released Minerva

On December 5, 2017, CERG released Minerva - Automated Hardware Optimization Tool, used for optimization and benchmarking of VHDL and Verilog implementations, targeting most recent families of FPGA devices. Minerva supplements ATHENa, our older generation hardware benchmarking tool, which supports Xilinx ISE, Altera Quartus II, and Intel Quartus Prime toolsets. The first version of Minerva aims specifically at the Xilinx Vivado toolset and Xilinx reconfigurable devices at and beyond the Series 7 families: Virtex-7, Kintex-7, Artix-7, and Zynq-7000. Minerva is based on a heuristic optimization algorithm aimed at finding optimum requested clock frequency and the best optimization strategy (one out of multiple sets of tool options, predefined in Xilinx Vivado), leading to either optimal throughput or optimal throughput-to-area ratio. The release of Minerva coincided with the presentation of the paper entitled "Minerva: Automated Hardware Optimization Tool," co-authored by members of CERG (Farnoud Farahmand, Ahmed Ferozpuri, William Diehl, and Kris Gaj), at the 2017 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, held in Cancun, Mexico, on December 4-6, 2017. (12/05/2017)


CERG released the Development Package and Implementer's Guide for Hardware Implementations Compliant with the CAESAR Hardware API, v.2.0

On December 5, 2017, CERG released the substantially extended and updated version 2 of the Development Package for Hardware Implementations Compliant with the CAESAR Hardware API, supplemented with the corresponding Implementer's Guide. The main new features include 1) full support for the development of lightweight implementations, optimized for minimum area, power, and energy per bit, 2) extended support for the development of high-speed implementations, covering all Round 2 and Round 3 CAESAR candidates, except Keyak, optimized for maximum throughput/area and throughput, 3) improved support for experimental testing using FPGA boards, in applications with intermittent availability of input sources and output destinations. The release of this package and guide is aimed at a) simplifying and speeding-up any future hardware development efforts for authenticated ciphers, b) making the developed cores easier to integrate into real-world systems, and c) accelerating the remaining phases of the CAESAR candidate evaluation. (12/05/2017)


Panasayya Yalla defended his Ph.D. Thesis

Panasayya Yalla defended his Ph.D. Thesis entitled "Methodology for Developing Lightweight Architectures for FPGAs," on December 1, 2017. Members of his Committee included: Dr. Kaps (Chair), Dr. Gaj, Dr. Mark, and Dr. Simon. (12/02/2017)


Duc Nguyen won 3rd place in the International Students' Olympiad in Cryptography NSUCRYPTO-2017

Duc Nguyen won third place in the International Students' Olympiad in Cryptography, NSUCRYPTO-2017, held on October 22-30, 2017. Duc participated in Round 2 for Professionals as a member of the team, including two of his colleagues from Ho Chi Minh City, Vietnam: Dat Bui Minh Tien and Quan Doan. The results of the competition were announced on December 1, 2017. Duc and his team repeated their 3rd place finish from 2016, but scored a higher percentage of the maximum score, 37 out of 60 (61.7%) in 2017 vs. 27 out of 64 (42.1%) in 2016. (12/01/2017)


GMU Team contributed an improved software implementation to the NIST submission package of the PQC candidate DAGS

Richard Haeussler and Duc Nguyen contributed an improved software implementation to the submission package of the Post-Quantum Cryptography algorithm DAGS. DAGS is a Key Encapsulation Mechanism (KEM) based on Quasi-Dyadic Generalized Srivastava codes. Its list of co-authors, specification, and software implementations are available at the DAGS project website. DAGS is one of 69 candidates qualified to Round 1 of the NIST PQC Standardization Process. (11/30/2017)


William Diehl gave a presentation at FPL 2017

William Diehl attended the 27th International Conference on Field-Programmable Logic and Applications, FPL 2017, held in Ghent, Belgium, on September 4-8, 2017. As part of this conference, William gave a short talk and presented a poster, entitled "Comparison of Hardware and Software Implementations of Selected Lightweight Block Ciphers," based on the paper co-authored with Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps and Kris Gaj. Additionally, William attended the workshop FPGAs for Software Programmers, FSP 2017, co-located with FPL. (09/08/2017)


Sanjay Deshpande spoke at DSD 2017

Sanjay Deshpande spoke at the Euromicro Conference on Digital System Design, held in Vienna, Austria, on August 30-September 1, 2017. He delivered an oral presentation entitled "Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates," co-authored with Kris Gaj. (09/02/2017)


CERG welcomed new members

At the end of August 2017, CERG welcomed new members: Viet Ba Dang who completed his BS degree in Electronics and Telecommunication at the Danang University of Science and Technology in Vietnam in 2016, Duc Tri Nguyen who completed his B.Eng in Computer Engineering at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Vietnam in 2015, and Chaitanya Neelamraju, who earned his Bachelor of Technology degree in Electronics & Communication Engineering (ECE) from Mahaveer Institute of Science & Technology, JNTUH in India in 2016. Viet and Duc will pursue their PhD degrees, and Chaitanya will work on his Master's thesis, all under the supervision of Dr. Gaj, with the focus on the area of post-quantum cryptography. (09/01/2017)


Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology:

Dr. Gaj gave an invited talk at the Ho Chi Minh City University of Technology (a.k.a. Bach Khoa University) in Ho Chi Minh City, Vietnam, on Aug. 16, 2017. His presentation was entitled "From AES to Post-Quantum Cryptography: FPGA Battles of Cryptographic Algorithms". It was attended by more than 30 faculty members and students from the Faculty of Computer Science and Engineering of the Bach Khoa University. (08/17/2017)


Presentation summarizing benchmarking of Round 3 CAESAR Candidates

The GMU Benchmarking Team has published and announced a comprehensive presentation, entitled "Benchmarking of Round 3 CAESAR Candidates in Hardware: Methodology, Designs & Results," made available at the CAESAR page of the ATHENa website. The GMU Team has contributed high-speed RTL implementations of AES-GCM and 11 Round 3 CAESAR Candidates. (08/11/2016)


Ahmad Salman defended his PhD Thesis

Ahmad Salman defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Kaps (Chair), Dr. Gaj , Dr. Homayoun , and Dr. Stavrou. In the middle of August 2017, Ahmad joined James Madison University in Harrisonburg, VA, as a tenure-track Assistant Professor. (2017/08/15)


Malik Umar Sharif defended his PhD Thesis

Malik Umar Sharif defended his PhD Thesis, entitled "Public Key Cryptography Using Hardware/Software Codesign for the Internet of Things," on August 2, 2017. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun , and Dr. Simon. Since March 2017, Umar has been already working as an FPGA Engineer at ixia, near Portland, OR. (2017/08/15)


Rabia Shahid defended her PhD Thesis

Rabia Shahid defended her PhD Thesis, entitled "A New Approach to the Development of Coprocessors for Pairing-based Cryptosystems," on July 31, 2017. The members of her dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Homayoun, and Dr. Albanese. In mid-August 2017, Rabia joined ixia, near Portland, OR, as an FPGA Engineer. (2017/08/15)


Dr. Gaj and Dr. Kaps attended PQCrypto 2017

Dr. Gaj and Dr. Kaps attended the 8th International Conference on Post-Quantum Cryptography, PQCrypto 2017, held in Utrecht, the Netherlands, June 26-28, 2017. During the Recent Result Session on June 26, chaired by Dr. Wouter Castryck, Dr. Gaj delivered a short presentation entitled "High-Speed Hardware for NTRUEncrypt-SVES: Lessons Learned", co-authored with Malik Umar Sharif. Additionally, Dr. Kaps attended a week-long Summer School on Post-Quantum Cryptography (organized by the H2020 project PQCRYPTO), and Dr. Gaj attended a two-day Executive School on Post-Quantum Cryptography (organized by the H2020 project ECRYPT-CSA). Both schools were held at the Technische Universiteit Eindhoven on June 19-23 and June 22-23, 2017, respectively. (06/29/2017)


Dr. Gaj spoke at CryptArchi 2017

Dr. Gaj spoke at the 15th International Workshop on Cryptographic Architectures Embedded in Logic Devices, CryptArchi 2017, held in Smolenice, Slovakia, on June 18-21, 2017. He delivered a talk entitled "Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems," co-authored with Malik Umar Sharif and Ahmed Ferozpuri. (06/22/2017)


Dr. Gaj spoke at the Workshop on Hardware Benchmarking 2017

Dr. Gaj spoke at the Workshop on Hardware Benchmarking, held in Bochum, Germany, on June 7, 2017. He delivered an invited talk entitled "Fair and Efficient Hardware Benchmarking of Candidates in Cryptographic Contests". (06/07/2017)


Rabia Shahid spoke at RAW 2017

Rabia Shahid spoke at the 24th Reconfigurable Architecture Workshop - RAW 2017, co-located with the 31st Annual IEEE International Parallel and Distributed Processing Symposium - IEEE IPDPS 2017, held in Orlando, Florida, on May 29-June 2, 2017. She delivered a talk entitled "A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems," based on the paper co-authored with Ted Winograd and Dr. Gaj. (06/01/2017)


Farnoud Farahmand earned internship at Google

Farnoud Farahmand has earned the position of the Hardware Engineer Intern at Google in Mountain View, CA, to be held between May 30 and August 25, 2017. (05/30/2017)


Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards

CERG Members, Ekawat Homsirikamol, Sanjay Deshpande, and Farnoud Farahmand received the 2017 Outstanding Academic Achievement Awards, handed to them by the ECE Department Chair, Prof. Monson Hayes, during the ECE Convocation Reception on May 18, 2017. Here is a photo of all awardees together with their academic advisor Dr. Gaj. (05/19/2017)


William Diehl qualified to the finals of the 3M Thesis Competition

William Diehl qualified to the finals of the 3-Minute Thesis competition. The preliminary round was held on March 3, 2017, in the HUB Rooms 4 & 5. 48 GMU doctoral students entered the contest, of whom 20 were from the Volgenau School of Engineering. Each contestant had three minutes (and one Powerpoint slide) to explain his/her research to a general audience. William was the only student representing CERG. The finals were held on Saturday, March 25, at Mason's Arlington Campus. They were part of the Mason Graduate Interdisciplinary Conference. An article about the competition, with a quote from William, was written by Martha Bushong, and published in News at Mason. The full video of his talk is available here. (03/06/2017)


Dr. Gaj's research featured in the Spring 2017 ECE Newsletter

Dr. Gaj's research has been featured in the Spring 2017 ECE Newsletter. The article about Dr. Gaj is called "Battles for Cryptographic Algorithms". (02/11/2017).