Benchmarking of Round 2 CAESAR Candidates
VHDL/Verilog Code of CAESAR Candidates: Summary I (last revised on July 23, 2016)
VHDL/Verilog Code of CAESAR Candidates: Summary II (last revised on July 23, 2016)
GMU Implementations of Authenticated Ciphers and Their Building Blocks
GMU Source Code of Round 2 CAESAR Candidates, AES-GCM, AES, AES-HLS, and Keccak Permutation F (last revised on July 22, 2016)
AES: Symbols, Block Diagrams, ASM Charts (posted on June 30, 2015)
Keccak Permutation F: Symbols, Block Diagrams, ASM Charts (posted on June 30, 2015)
CAESAR Hardware API v1.0
CAESAR Hardware API, full specification, v1.0 (last revised on May 12, 2016; posted on ePrint on June 17, 2016)
Addendum to the CAESAR Hardware API v1.0 (last revised on June 10, 2016)
Implementer's Guide to the CAESAR Hardware API, v1.1 (last revised on June 10, 2016)
Verilog/VHDL Code: Suggested List of Deliverables, v1.0 (posted on June 20, 2016)
Rules for Reduced Complexity Block Diagrams, by William Diehl, v1.0 (posted on June 20, 2016)
GMU Hardware API v1.2 (superseded by CAESAR Hardware API v1.0)
GMU Hardware API for Authenticated Ciphers, full specification (last revised on December 6, 2015)
Supporting Files for High-Speed Implementations v1.2 (last revised on December 6, 2015)
The most recent alpha version is version 0.6.5.
This version was posted on October 7, 2014 and is available below in two variants:
The corresponding tutorial (also included in the zip files) is available here:
The History of Changes since ATHENa 0.6 is listed at the end of the Tutorial.
Below we list our development plan from version 0.1 to version 1.0.
0.1 - support for Xilinx FPGAs in a single_run mode;
placement_search - automated search for an optimum placement
starting point (optimum value of a cost table)
0.2 - support for Altera FPGAs
0.3 - exhaustive search for optimum options of synthesis and implementation tools, enhanced error handling capability
0.4 - new enhanced ATHENa setup, support for multi-core processing, automated verification of designs through functional simulation run in batch mode, enhanced progress reports
0.5 - new heuristic optimization algorithms: frequency_search and GMU_Xilinx_optimization_1; spooler script
0.6 - support for Linux, new heuristic optimization strategy: GMU_optimization_1, iteration through multiple values of generics, new FPGA families (Spartan 6, Virtex 6, Cyclone IV, Stratix IV, Arria families), support for Verilog and AHDL, support for using ATHENa with Altera MegaWizard Plug-in Manager and Xilinx CORE Generator, data trimming mode, database report generator, support for purely combinational circuits, capability to create replication files that can be used to regenerate optimized results without using ATHENa, tutorial converted to LaTeX.
0.7 - automated verification of designs through post-synthesis and timing simulation in batch mode
0.8 - support for Microsemi (formerly Actel) FPGAs
0.9 - additional heuristic optimization algorithms
1.0 - accommodating comments received by users testing earlier versions.
We reserve the right to introduce changes to this development
The timeline of the project will depend on the future availability of human resources, funds, and contributions by volunteers interested in co-developing the system.
Current and earlier versions of the environment have been (or
will be) extensively tested by students taking the following
graduate classes at George Mason University:
ECE 545 Digital System Design with VHDL
Fall 2014: ECE 545 Digital System Design with VHDL
Fall 2012: ECE 545 Digital System Design with VHDL
Spring 2012: ECE 645 Computer Arithmetic
Fall 2011: ECE 545 Digital System Design with VHDL
Spring 2011: ECE 645 Computer Arithmetic, ECE 746 Applied Advanced Cryptography
Fall 2010: ECE 545 Digital System Design with VHDL, ECE 646 Cryptography and Computer Network Security