Ekawat (Ice) Homsirikamol

Contact

George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
 Office: Engineering Building, Room 3231
Phone (lab): 703-993-1609
E-Mail: ehomsiri'at'gmu.edu
Curriculum Vitae: Ekawat Homsirikamol

Research Interests

  • FPGA-based embedded systems, particularly in the area of applied cryptography
  • Design and analysis of hardware implementation of cryptographic algorithms
  • Hardware design optimization and automation
  • High level synthesis
  • Reconfigurable computing

Advisor: Dr. Kris Gaj

Biography

Ekawat graduated from George Mason University with the Ph.D. degree in Electrical and Computer Engineering in Fall 2016. He received his M.S. in Computer Engineering from GMU in 2010. He also received his B.S. in Electrical Engineering degree from GMU in 2008.

Publications

  • J.-P. Kaps, W. Diehl, M. Tempelmeier, F. Farahmand, E. Homsirikamol, and K. Gaj, A comprehensive framework for fair and efficient benchmarking of hardware implementations of lightweight cryptography, Nov, 2019, Cryptology ePrint Archive, Paper 2019/1273 [Bibtex]
  • K. Mohajerani, M. Tempelmeier, F. Farahmand, E. Homsirikamol, W. Diehl, J.-P. Kaps, and K. Gaj, Implementers guide to hardware implementations compliant with the hardware API for lightweight cryptography, v1.2.0, Feb, 2022 [pdf] [Bibtex]
  • J.-P. Kaps, W. Diehl, M. Tempelmeier, E. Homsirikamol, and K. Gaj, Hardware API for lightweight cryptography v1.1 (with support for SCA-protected implementations), Jan, 2022 [pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, Dec, 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]
  • E. Homsirikamol and K. Gaj, Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 217-228, Apr, 2015 [Bibtex]
  • E. Homsirikamol and K. Gaj, Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study., 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2014, IEEE, pages 1–8, Dec., 2014 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]
  • P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wójcik, ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption, Cryptographic Hardware and Embedded Systems, CHES 2014, LNCS, volume 8731, Springer Berlin Heidelberg, pages 392–413, Sep., 2014 [Bibtex]
  • M. Rogawski, E. Homsirikamol, and K. Gaj, A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs, 24th International Conference on Field Programmable Logic and Applications – FPL 2014, IEEE, pages 1–8, Sep., 2014 [Bibtex]
  • M. Rogawski, K. Gaj, and E. Homsirikamol, A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl, Microprocessors and Microsystems, volume 37, number 6-7, pages 572-582, 2013 [Bibtex]
  • B. Brewster, E. Homsirikamol, R. Velegalati, and K. Gaj, Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules, 2012 International Conference on Field Programmable Technology - FPT, Dec, 2012 [Bibtex]
  • S. Paul, E. Homsirikamol, and K. Gaj, A Novel Permutation-based Hash Mode of Operation FP and The Hash Function SAMOSA, 13th International Conference on Cryptology in India - Indocrypt, Dec, 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Jun., 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex]
  • F.K. Gürkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASICfor evaluating third round SHA-3 candidates, Mar, 2012 [pdf] [Bibtex]
  • E. Homsirikamol, Fair and comprehensive comparison of hardware performance of SHA-3 round 2 candidates using FPGAs, George Mason University, 2010, Masters' Thesis [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Throughput vs. Area trade-offs architectures of five Round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs, Workshop on Cryptographic Hardware and Embedded Systems CHES 2011, LNCS, volume 6917, Springer Berlin / Heidelberg, pages 491–506, Sep, 2011 [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs, 2010, Cryptology ePrint Archive, Report 2010/445 [pdf] [Bibtex]
  • K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, and B.Y. Brewster, ATHENa – automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs, 20th International Conference on Field Programmable Logic and Applications - FPL 2010, IEEE, pages 414–421, 2010 [accepted version, pdf] [Bibtex]
  • K. Gaj, E. Homsirikamol, and M. Rogawski, Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGA, Cryptographic Hardware and Embedded Systems, CHES 2010, LNCS, volume 6225, Springer Berlin / Heidelberg, pages 264–278, 2010 [Bibtex]

Note: See CV for full list of publications.