CERG Seminars are held in the Engineering Building on the GMU Fairfax campus unless noted otherwise. Parking is available in the Sandy Creek parking deck near the Engineering Building. Directions to the campus can be found here. The seminar talks are usually 45 to 60 minutes long and are open to the public. If you wish to be notified about future seminars, please send an e-mail to Jens-Peter Kaps.

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Homomorphic Cryptography Survey

David Arrlen, MS CpE Scholarly Paper
Date: Monday, April 30th, 5:00 PM, Location: Engineering Building, Room 3507


Homomorphic cryptography provides a means of performing mathematic operations in both the ciphertext and plaintext domains with correct results in each. Mobile devices have many limitations due to their low power design requirements that make offloading computations to the cloud desirable. The cloud is an untrusted computing resource and therefore should not have access to sensitive data. Using a homomorphic cryptosystem, the mobile device can send sensitive operands in encrypted form to the cloud for computation and decrypt the result received from the cloud. This paper discusses previous work from Rivest's first publication on the subject to Gentry's fully homomorphic cryptosystem as well as applications thereof.

PCI Express Interface for High Performance FPGA Boards

Patrick Daderko, MS CpE Scholarly Paper
Date: Monday, April 30th, 3:30 PM, Location: Engineering Building, Room 3507


PCI Express (PCIe) has become a common standard in computing, providing a versatile high-speed communication bus. Many high performance FPGA boards utilize PCIe for communication, which provide opportunities and challenges for engineers. Specific development and application boards using Xilinx Virtex 6 and Altera Stratix IV FPGAs will be compared, reviewing connectivity, on-board hardware resources, and other details.

There will also be discussion of PCIe FPGA IP cores, drivers, and API software. Specifically, Jungo WinDriver, a cross-platform and cross-device driver development software, will be described, analyzed, and compared to other offerings available. IP cores from Xilinx and Altera, as well as Northwest Logic and PLDA will also be described and compared.

Included in all topics will be discussion of performance, resources, price, development time and effort, and related details.

Market Survey of Low Powered FPGA Devices

Aditya Mehta, MS CpE Scholarly Paper
Date: Monday, April 30th, 1:00 PM, Location: Engineering Building, Room 3507


Field Programmable Gate Arrays (FPGAs) have been gaining popularity due to their much lower non-recurring cost and their attractive cost/performance ratio in electronic products. Furthermore, the recent advent of low-power FPGAs for battery powered devices has spurred this trend. Hence they are being employed on a large scale in many designs. Designers have traditionally relied on application-specific integrated circuits (ASICs), not FPGAs, to meet their low-power constraints. With longer time-to-market, rising non-recurring engineering charges (NREs), and a lack of flexibility to address changing standards and late-stage design modifications, hardwired ASICs are riskier and often impractical for applications with short product life cycles.

This presentation surveys the many low powered FPGAs that are available in the market currently. The vendors surveyed are Xilinx, Microsemi, Lattice Semiconductor, Altera and SiliconBlue Technologies (a Lattice Semiconductor Company). An analysis of the technologies that are used to make sure these FPGAs consume as little power as possible is made, and a comparison of the different low power features available on these FPGAs. Each FPGA vendor offer different intellectual property (IP) cores for their FPGAs like processor IP cores, interface/bus/bridge IP, peripheral IP or Communications IP. This presentation will discuss some of the different IP cores offered by the vendors.

Distributed Computing and Optimization Space Exploration for Fair and Efficient Benchmarking of Cryptographic Cores in FPGAs

Benjamin Brewster, MS CpE Master's Thesis Defense
Date: Monday, April 30th, 10:00 AM, Location: Engineering Building, Room 3507


Benchmarking of digital designs targeting FPGAs is a time intensive and challenging process. Benchmarking results depend on a myriad of variables beyond the properties inherent to the designs being evaluated, encompassing the tools, tool options, FPGA families, and languages used. In this thesis we will be discussing enhancements made to the ATHENa benchmarking tool to utilize distributed computing as well as optimization space exploration techniques to increase the efficiency of the ATHENa benchmarking process. Capabilities of the environment are demonstrated using four example designs from the SHA-3 cryptographic hashing function competition, BLAKE, JH, Keccak and Skein.

SHA-3 Finalist Keccak on FPGAs

Smriti Gurung, MS CpE Master's Thesis Defense
Date: Friday, April 27th, 11:00 AM, Location: Engineering Building, Room 3202


The Secure Hash Algorithm (SHA) is a cryptographic hash function published by the National Institute of Standard and Technology (NIST) as a U.S Federal Information and Processing Standard (FIPS). In the past few years, a flaw discovered in the SHA-1 shows its vulnerability to attacks. The current hashing standard SHA-2 which shares similarities to SHA-1 is therefore under scrutiny for a possible attack. In 2007, NIST announced the SHA-3 competition in hopes of finding a new algorithm with higher margin of security and which is also more efficient in terms of software and hardware performance. Out of the 51 candidates selected in round one, only five remain in the third and final round namely BLAKE, Grostl, JH, Keccak and Skein.

So far, several high speed implementations of the SHA-3 algorithms on FPGAs have been published. However, these implementations become impractical for resource constrained environments where area is a limitation for e.g small battery powered hand held devices. Our goal was to design different lightweight architectures for the sponge construction based algorithm Keccak. We tried to evaluate its performance with respect to its scalability. In this study all the implementations were designed with an area constraint of 800 slices or 400-600 slices and one block RAM, targeting the low cost Spartan-3 devices. Designs were also synthesized on different Xilinx and Altera devices for comparison with other published results. Although our implementation of Keccak is one of the smallest reported so far, this reduction came at the cost of lower throughput to area ratio.