CERG Seminars are held in the Science and Technology II building on the GMU Fairfax campus unless noted otherwise. Parking is available in the Sandy Creek parking deck just to the side of Science and Technology II. Directions to the campus can be found here. The seminar talks are usually 45 to 60 minutes long and are open to the public. If you wish to be notified about future seminars, please send an e-mail to Jens-Peter Kaps.
Seminar: Mersenne Twister - A Pseudo Random Number Generator and its variants
Archana Jagannatam, MS CpE Scholarly Paper Presentation
Date: Friday, November 21st, 3:30 pm, Location: Science and Technology II (ST-II), Room 230A
Random number generators(RNG) are widely being used in number of applications, particularly simulation and cryptography. They are a critical part of many cryptographic systems such as key generation, initialization vectors, message padding, nonces and many more. This paper discusses about the Mersenne Twister(MT), a pseudo random number generator(PRNG) and its variants. It mainly emphasizes on two of its variants. SIMD-Oriented Fast Mersenne Twister(SFMT) which is a 128-bit PRNG analogous to MT making full use of its features. And the cryptographically secure CryptMT, considered to be one of the fastest stream ciphers on a CPU with SIMD operations. It also briefly discusses the theories and the choice of parameters used in the algorithms. The requirements for a PRNG to be certified as a good and cryptographically secure PRNG will be presented.
Seminar: Comparative Analysis of T-box vs. S-box hardware architectures of Advanced Encryption Standard (AES)
Nitin Alabur, MS CpE Scholarly Paper Presentation
Date: Thursday, July 31st, 11:30 pm, Location: Science and Technology II (ST-II), Room 230A
AES is a cipher that has been analyzed extensively and standardized by NIST. The algorithm has been implemented with an S-box architecture which has smaller memory requirement but lower throughput due to four separate operations of shift rows, sub bytes, mix columns and add round key. The cipher has also been implemented with a Tbox architecture, where the shift rows, sub bytes and the mix columns operations are performed by a single table look up. The implementation with T-box architecture has a higher throughput since there are only two operations (a look up and add round key) to be performed for every iteration and more area due to the large memory required to store the larger look up tables.
This paper will discuss the hardware implementation of AES with T-box architecture, with a key scheduling scheme that stores the precomputed round keys in the memory. It compares the T-box implementation results with the S-box and with the results obtained by Viktor Fischer and Milos Drutarovsky for the key sizes 128, 192 and 256 bits. The implementations are targeted on Xilinx Spartan3 and Virtex5 FPGAs.
Seminar: Hardware architectures of AES Key Scheduling Schemes
Bhupathi V. N. Kakarlapudi, MS CpE Scholarly Paper Presentation
Date: Thursday, July 31st, 10:30 pm, Location: Science and Technology II (ST-II), Room 230A
Advanced Encryption Standard (AES) is a FIPS approved cryptographic algorithm used to protect electronic data. AES is a symmetric block cipher with a data length of 128 bits and variable key length of 128, 192 and 256 bits.
Many AES architectures were proposed in the literature, where the key scheduling scheme was implemented either as 'On-the-fly' key schedule or as 'In-advance' precomputation of sub-keys. Choice of key scheduling scheme is particularly interesting because one scheme increases the computation time and the other requires storage of keys in memory thereby increasing the area and initial latency. This paper discusses these two schemes of key scheduling and their hardware architectures that can output key in block length sizes of 128, 64, and 32 bits per clock cycle and also to discuss the architectures which can support all the key sizes, also known as 3-in-1 model.
Seminar: FPGA Implementation of high throughput circuit for 256 and 512 bit numbers involving small primes
Keerat Brar, MS EE Scholarly Paper Presentation
Date: Thursday, July 31st, 1:00 pm, Location: Science and Technology II (ST-II), Room 230A
Factorization is one of the important components of Number Theory. Since many cryptographic systems depend on prime numbers studies, such as factoring, and related number-theoretical problems, technological and algorithmic advancement have become very important. The difficulty of factoring large integers is the basis of the RSA encryption algorithm. Several special purpose hardware devices have been implemented which are capable of factoring a large numbers with high throughputs. These machines can be designed to be implemented of ASICs or FPGAs. One such factorization algorithm is the Trial division sieve algorithm. It is one of the most popular ways to factor large numbers. However, the execution time for factorization is dependent on the size of the number. We developed an FPGA implementation of a high throughput trial divisions sieve circuit for a 256-512 bit number involving small primes with a bound of 10,000.
Seminar: Implementation and Comparative Analysis of AES as a STREAM Cipher
Bin Zhou, MS CpE Scholarly Paper Presentation
Date: Friday, July 25th, 1:00 pm, Location: Science and Technology II (ST-II), Room 230A
Advanced Encryption Standard (AES) is the current encryption standard adopted by U.S. government, which plays an important role in today's cryptographic systems. AES is usually considered a block cipher; however, by using different operating modes, it can be easily turned into a stream cipher. Nevertheless, how well AES could perform as a stream cipher in a resource restricted environment compared to other modern stream ciphers has remained unclear. In this paper, the motivation for implementing AES as a stream is introduced. On-the-fly key scheduling schemes are used and various compact architectures are studied. Pure logic based and ROM based S-Boxes are implemented for the purpose of comparison in terms of speed and area. Pipelined architecture is also studied in order to achieve a better throughput. Different memory schemes are considered, including 2-bank distributed RAM, 2-bank block RAM, shift-register in LUTs, 1-bank registers and dual-port memory. 8-bit, 32-bit, 64-bit datapath versions are implemented in order to find the architecture with the best throughput/area ratio. The whole design is targeted to Xilinx Spartan 3 FPGAs, and developed with synthesizable VHDL code. The performance results are compared with eSTREAM cipher candidates and also with other implementations of AES, showing that our implementation
ECE 746 Secure Telecommunication Systems, Final Project Presentations
Date: Monday, May 12th, 6:00 pm - 10:00 pm, Location: Student Union Building II (SUB II), Rooms 5 & 6
The exact schedule is posted here and the complete specification of each project is available here. All final reports and presentations, and results of the contest for the best project will be published on the same web page at a later date.
Four members of our research group, Ted, Rajesh, Panasayya, and Bin, will be presenting on Monday. Please come over to cheer them on! Sweets and beverages will be provided to celebrate the end of the busy semester.
Security analysis and new composition of broadcast authentication for wireless sensor networks
Prof. Taekyoung Kwon , Sejong University, Seoul, Korea
Date: Friday, May 2nd, 11 am - 12 noon, Location: Science and Tech II, Room 100
In this talk, I would like to present the recent result of security analysis and new composition of broadcast authentication for wireless sensor networks. Technological advancement in large scale distributed networking and small lowpowered sensor devices has led to the development of wireless sensor networks in unattended and even hostile environments. Such networks may need broadcast authentication for allowing a based station to send commands and requests to distributed sensor nodes in an authentic manner. The well known broadcast authentication schemes based on the delayed exposure of one-way key chains are devised for efficiency in resource-limited sensor nodes. This talk firstly shows that such schemes with 64-bit key chains (desired for efficiency) disclose partial future keys through time memory data tradeoff techniques, and become severely less efficient in computation and buffer occupation for possible sleep modes, network failures, and idle sessions of networks. Secondly, a new scheme is presented for resolving those problems by composing two levels of chains that have distinct intervals and mutually authenticate each other. This allows the short key chains to continue indefinitely and efficiently for sensor nodes, and makes new interesting strategies and management methods possible. The talk will be given mostly in abstract but some concrete results will be shown.
(1988-1999) BS, MS, and Ph.D. in Computer Science, Yonsei University, Seoul, Korea
(1999-2000) PostDoc at U.C. Berkeley - funded by KOSEF and Samsung Electronics
(2001-present) Associate Professor in Computer Eng., Sejong University, Seoul, Korea
(2007-present) Visiting Research Associate at UMD. (working with Prof. Virgil Gligor)
Implementation and Comparative Analysis of Selected Modern Hardware Architectures for Montgomery Multiplication
Ryon Sumner, Scholarly Paper and Research Project Presentation
Date: Thursday, April 24th, 5 pm - 6 pm, Location: Science and Tech II, Room 330 A
With several modern public key cryptographic algorithms (e.g. RSA) based on modular exponentiation, hardware implementations of these algorithms focus on performing exponentiation efficiently. One method of performing modular exponentiation quickly is based on the elementary operation called Montgomery Multiplication. This algorithm has become popular as it replaces expensive multiplications and modular reductions with much simpler conditional additions and shifts.
This paper focuses on comparative analysis of several classical and most recent hardware architectures for Montgomery Multiplication and Montgomery Exponentiation. All analyzed architectures have been modeled in VHDL and implemented using Xilinx FPGA devices. A method for performing a fair comparison between the competing designs has been developed. All architectures have been evaluated based on their maximum clock frequency, overall area (in terms of CLB slices) and the total latency, in order to highlight the strengths and weaknesses of each solution.
Efficient Software Implementations of Elliptic Curve and Pairing-based Digital Signatures over Binary Field
John Gibson, MS CpE Thesis defense
Date: Thursday, April 24th, 6 pm - 7 pm, Location: Science and Tech II, Room 330 A
Digital signatures play an important role in the modern connected world. They underpin a variety of electronic transactions, from signed email messages to the web site certificates that protect countless dollars of e-commerce and sensitive information. The majority of digital signatures used today are based on RSA and the security of factoring large numbers, but to keep secure against faster processing and more complex attacks, these numbers have become increasingly large. This has caused the focus to shift toward digital signatures using elliptic curve cryptosystems such as ECDSA, which can provide similar security while using much smaller key sizes. Cryptographic pairings over elliptic curves are currently a hotbed of research activity and they are used to construct new protocols, most notably identity-based cryptosystems. Digital signature protocols, such as the BLS short signature scheme, have been devised using pairings.
In this thesis, software implementations of elliptic curve and pairing-based digital signatures are compared using different underlying open source cryptographic software libraries. In addition, scalar multiplication and the pairing, the main operations that support these protocols, are examined. To enable the investigation of the BLS signatures, implementations of the Eta pairing on elliptic curves over binary fields were created and explored. The performance differences between different variants of the pairing and underlying libraries are contrasted and compared to the results of hardware designs from other research. As part of this effort, ECClib, an elliptic curve software library developed at George Mason University was extended to handle pairing-friendly curves and the Eta pairing algorithm. To facilitate performance testing, the BATMAN benchmarking program was used to measure the differences of the digital signature protocols and the underlying operations (scalar multiplication and pairings). Software profiling and examination of source code is used to further analyze the differences in performance between the libraries.