Rajesh Velegalati


3100 Engineering Building
George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
Office: Engineering Building , Room 3224
Phone (lab): 703-993-1561
E-Mail: rvelegal'at'gmu.edu
Personal Homepage: http://mason.gmu.edu/~rvelegal/

Research Interest

  • Side Channel Analysis
  • Protection against side channel attacks
  • Tamper sensing circuits
  • Dynamic Reconfiguration
  • Theoretical aspects of SCA
  • Ultra Low Power Cryptographic Implementation
  • Devoloping Back end tools for FPGAs

Advisor: Dr. Jens-Peter Kaps


Rajesh received his Master Degree from George Mason University in Summer 2009 and received his Bachelor Degree from Sir C.R.Reddy College on Engineering, Andhra University, India in 2006. He started his Phd program in George Mason University in Fall 2009. He is a research assistant under Dr. Jens-Peter Kaps as a part of CERG.


  • R. Velegalati and R. Van, Electro Magnetic Fault Injection in Practice, Sep, 2013, The First International Cryptographic Module Conference, ICMC 2013 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS), June, 2013, Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI 2013 [pdf] [Bibtex]
  • R. Velegalati, K. Shah, and J.-P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, 2013 Euromicro Conference on Digital System Design (DSD), pages 947–954, 2013 [Bibtex]
  • B. Brewster, E. Homsirikamol, R. Velegalati, and K. Gaj, Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules, 2012 International Conference on Field Programmable Technology - FPT, Dec, 2012 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis, May, 2012, Work in Progress (WiP), Third International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2012 [pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [pre-print, pdf] [Bibtex]
  • S. Shah, R. Velegalati, J.-P. Kaps, and D. Hwang, Investigation of DPA resistance of Block RAMs in cryptographic implementations on FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'10, IEEE, pages 274–279, Dec, 2010 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic, International Conference on Electronics, Circuits, and Systems, ICECS 2010, IEEE, pages 1251–1254, Dec, 2010 [pre-print, pdf] [Bibtex]
  • J.-P. Kaps and R. Velegalati, DPA resistant AES on FPGA using partial DDL, IEEE Symposium on Field-Programmable Custom Computing Machines – FCCM 2010, IEEE, pages 273–280, May, 2010 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 385–390, Aug, 2009 [, pdf] [Bibtex]


  • R. Velegalati, Securing light weight cryptographic implementations on FPGAs using dual rail with pre-charge logic, ECE Department, George Mason University, Fairfax, Virginia, USA, July, 2009, Master's Thesis [Bibtex]

Technical Reports

  • R. Velegalati and P. Yalla, Differential power analysis attack on FPGA implementation of AES, George Mason University - ECE Department, May, 2008 [pdf] [Bibtex]