Marcin Rogawski

Contact

George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
Office: Engineering Building II, Room 3231
Phone (lab): 703-993-1609
E-Mail: mrogawsk'at'gmu.edu
Curriculum Vitae: Marcin Rogawski
Personal Homepage: http://mason.gmu.edu/~mrogawsk/

Research Interest

  • Reconfigurable Computing
  • Efficient implementations of crypto algorithms and security protocols in programmable logic
  • Elliptic and Hyperelliptic Curve Cryptography
  • Pairing based Cryptography
  • Design of block and stream ciphers
  • Linear, differential cryptanalysis and Algebraic attacks
  • IPSec and other Applications of Cryptogrpahy
  • Micorocontroller development
  • Implementations of Operating Systems

Advisor: Dr. Kris Gaj

Biography

Marcin is a Research Assistant in the Electrical and Computer Engineering Department at GMU. He is working toward his PhD degree in Computer Engineering as part of CERG. He received his M.S. degree from Military University of Technology.

Publications

  • M. Rogawski and K. Gaj, A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grostl, 15th EUROMICRO Conference on Digital System Design – DSD 12, 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Jun., 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex]
  • F.K. G"urkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates, Mar, 2012 [pdf] [Bibtex]
  • R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Throughput vs. Area trade-offs architectures of five Round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs, Workshop on Cryptographic Hardware and Embedded Systems CHES 2011, LNCS, volume 6917, Springer Berlin / Heidelberg, pages 491–506, Sep, 2011 [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of five round three SHA-3 candidates, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]
  • K. Gaj, E. Homsirikamol, and M. Rogawski, Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGA, Cryptographic Hardware and Embedded Systems, CHES 2010, LNCS, volume 6225, Springer Berlin / Heidelberg, pages 264–278, 2010 [Bibtex]
  • K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, and B.Y. Brewster, ATHENa – automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs, 20th International Conference on Field Programmable Logic and Applications - FPL 2010, IEEE, pages 414–421, 2010 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol, M. Rogawski, and K. Gaj, Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs, 2010, Cryptology ePrint Archive, Report 2010/445 [pdf] [Bibtex]