Post-Quantum Cryptography in Hardware and Embedded Systems
Major investments by national governments and high-tech companies have led to first demonstrations of quantum supremacy, i.e., computations conducted by a quantum computer that no classical computer can perform in any feasible amount of time. The goal of this project is to support NIST in its effort to develop a new generation of public-key cryptographic standards, resistant against quantum computers, a.k.a. NIST Post-Quantum Cryptography (PQC) Standardization Process. In Rounds 1 and 2 of this effort, the assessment of PQC candidates has focused primarily on their security and software efficiency. Our aim is to set the foundation for the early, systematic, and comprehensive study of the hardware and embedded system efficiency of the most promising PQC candidates. The next 5-10 years are very likely to bring the biggest revolution in cryptography, since the invention of public-key cryptography in mid-1970s. This project gives us a unique opportunity to influence the choice of future cryptographic standards, which are likely to be developed and deployed within the next decade and remain in use for the significant portion (if not the rest) of the 21st century.
Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.
Job Announcements:
GRA Positions in Post-Quantum Cryptography
CERG is seeking qualified candidates for multiple Graduate Research Assistant positions in the area of efficient implementations of Post-Quantum Cryptosystems, side-channel attacks targeting these cryptosystems, and countermeasures against such attacks. The desired qualifications include strong mathematical background in algebra and number theory, experience in hardware design using hardware description languages, and knowledge of C and scripting languages, such as Python. Additional experience in Magma or SageMath, ASIC or FPGA design, software/hardware codesign, High-Level Synthesis, embedded software development, and/or circuit/PCB design, and Linux operating system is a plus.
All positions are open starting in January or August 2025. Qualified candidates should apply to the ECE PhD program at George Mason University, indicating Dr. Gaj and/or Dr. Kaps as possible future advisors. In parallel, an earlier e-mail contact with Dr. Gaj and/or Dr. Kaps is highly recommended.
Latest News:
Dr. Gaj will give a keynote speech at C3iHub's Conference on Emerging Trends in Cybersecurity
Dr. Gaj will give a keynote speech titled "Hardware Implementations of Post-Quantum Cryptography Schemes: Past, Present, and Future" at C3iHub's Conference on Emerging Trends in Cybersecurity, CCETC 2024, to be held at IIT Kanpur, India, on October 22-25, 2024. To learn more about the C3iHub, please view a short video available here. (10/14/2024)
Dr. Gaj gave an invited talk at the Deployment of Post-Quantum Cryptography workshop
Dr. Gaj gave an invited talk titled "Hardware Implementations of PQC KEMs and Digital Signature Schemes" at the Deployment of Post-Quantum Cryptography workshop, held at the Institut Henri Poincare (IHP) in Paris on October 7-11, 2024. The workshop was a part of the thematic trimester program at IHP on post-quantum cryptography, held from September 9 to December 13, 2024 (10/12/2024)
Dr. Gaj serves as a member of the Program Committee of DATE 2025
Dr. Gaj serves as a member of the Program Committee of DATE 2025: Design, Automation and Test in Europe conference, in Track A: Application Design, Topic A3: Secure Systems, Circuits, and Architectures. Multiple student members of CERG are contributing their time and expertise, serving as sub-reviewers for the track and topic mentioned above. The virtual TPC Meeting will be held on November 12, 2024. (09/26/2024)
Dr. Kaps gave a talk at OPTIMIST 2024 and attended CHES 2024
Dr. Kaps gave a talk titled "Hardware API for Lightweight Cryptography" based on work by Kamyar Mohajerani, Jens-Peter Kaps, and Kris Gaj at the Open Tools, Interfaces and Metrics for Implementation Security Testing (OPTIMIST) 2024 workshop held in Halifax, Canada on September 4th, 2024. This workshop is affiliated with the Conference on Cryptographic Hardware and Embedded Systems (CHES), held in the same location from September 4-7, which Dr. Kaps attended. (09/08/2024)
Dr. Gaj gave a keynote speech at CryptoIC 2024
Dr. Gaj gave a keynote speech at CryptoIC 2024, held in Chengdu, China, on August 10-11, 2024. His talk was titled "Hardware Implementations of Post-Quantum Cryptography Digital Signature Schemes." CryptoIC is a conference held annually by the Cryptographic IC Technical Committee, Chinese Association for Cryptologic Research. It is attended by more than 300 researchers from academia, industry, and research institutes. (08/12/2024)
Kamyar Mohajerani defended his Ph.D. Thesis Proposal
Kamyar Mohajerani defended his Ph.D. Thesis Proposal, titled "Efficient and Secure Hardware Implementation of Cryptographic Algorithms," on July 26, 2024. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Sai Manoj PD, and Dr. Zhang. (07/27/2024)
Miguel Medina Anton defended his MS Thesis
Miguel Medina Anton defended his Master's Thesis, titled "Hardware Implementation of the FAEST PQC Digital Signature Scheme," on July 25, 2024. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, and Dr. Manoj PD. The thesis was developed in partial fulfillment of the requirements for the degrees of Master of Science in Computer Engineering at George Mason University and Master of Science in Telecommunication Engineering at Universidad Politecnica de Madrid (UPM). (07/26/2024)
CERG paper to appear in the Special Issue of ACM Transactions on Embedded Computing Systems
The CERG paper titled "Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process," by Kamyar Mohajerani, Luke Beckwith, Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj, will appear in the Special Issue of ACM Transactions on Embedded Computing Systems devoted to Open Hardware for Embedded System Security and Cryptography. The paper was accepted on May 16, 2024 and was published online on July 17, 2024. (07/18/2024)
Ted Winograd defended his Ph.D. Thesis
Ted Winograd defended his Ph.D. Thesis, titled "A New Approach to the Development of Cryptographic Hardware Based on Specialized Computer-Aided Design Tools," on April 24, 2024. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh, and Dr. Barua. (04/25/2024)
Members of CERG attended the Fifth PQC Standardization Conference
Five members of CERG, Luke Beckwith, Kamyar Mohajerani, Miguel Medina Anton, Dr. Gaj, and Dr. Kaps attended the Fifth PQC Standardization Conference, organized by NIST in Rockville, Maryland, on April 10-12, 2024. (04/13/2024).
Dr. Kaps gave a talk at the ASHES 2023
Dr. Kaps gave a talk titled "FOBOS 3: An Open-Source Platform for Side-Channel Analysis and Benchmarking," at Attacks and Solutions in Hardware Security (ASHES) 2023, a post-conference satellite workshop of the 30th ACM Conference on Computer and Communications Security, CCS 2023, held in Copenhagen, Denmark on November 26-30, 2023. This talk was based on the paper authored by Eduardo Ferrufino, Luke Beckwith , Abubakr Abdulgadir , and Jens-Peter Kaps. (12/01/23).
CERG welcomed new members
At the end of August 2023, CERG welcomed new members: Miguel Medina Anton, who completed his Bachelor of Engineering Technology degree in Telecommunications at the Universidad Politecnica de Madrid (UPM) in Spain in 2022, and Ayomikun Akindahunsi, who completed his BS degree in Computer Engineering at the University of Alabama in Huntsville in 2023. Miguel and Ayomikun will work on their Master's theses under the supervision of Dr. Gaj, with a focus on the area of post-quantum cryptography. (09/01/2023)
Luke Beckwith and Robert Wallace spoke at PQCrypto 2023
Luke Beckwith and Robert Wallace gave a talk titled "A High-Performance Hardware Implementation of the LESS Digital Signature Scheme" at the 14th International Conference on on Post-Quantum Cryptography, PQCrypto 2023, held at the University of Maryland, College Park, MD, USA, on August 16-18, 2023. This talk was based on the paper co-authored with Kamyar Mohajerani, and Kris Gaj. (08/19/2023)
CERG paper to appear in the Special Issue of IEEE Design & Test
The CERG paper titled "Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON," by Luke Beckwith, Duc Tri Nguyen, and Kris Gaj, will appear in the Special Issue of the IEEE Design & Test magazine devoted to Post-Quantum Cryptography for Internet-of-Things (IoT). The paper was published online on August 14, 2023. (08/15/2023)
Latest publications:
Copyright Notice
The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.
- L. Beckwith, D.T. Nguyen, and K. Gaj, Hardware accelerators for digital signature algorithms dilithium and falcOn, IEEE Design and Test, volume 41, number 5, pages 27–35, Oct., 2024 [Bibtex]
- K. Mohajerani, L. Beckwith, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Lightweight champions of the world: Side-channel resistant open hardware for finalists in the NIST lightweight cryptography standardization process, ACM Transactions on Embedded Computing Systems, Jul., 2024 [Bibtex]
- E. Ferrufino, L. Beckwith, A. Abdulgadir, and J.-P. Kaps, FOBOS 3: An open-source platform for side-channel analysis and benchmarking, Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security (ASHES), Association for Computing Machinery, Copenhagen, Denmark, pages 5–14, Nov, 2023 [pdf] [Bibtex]
- L. Beckwith, R. Wallace, K. Mohajerani, and K. Gaj, A high-performance hardware implementation of the LESS digital signature scheme, 14th International Conference on Post-Quantum Cryptography, PQCrypto 2023, College Park, MD, LNCS, volume 14154, Springer, pages 57-90, August, 2023 [Bibtex]
- D.T. Nguyen and G. Kris, Fast Falcon signature generation and verification using ARMv8 NEON instructions, 14th International Conference on Cryptology, AFRICACRYPT 2023, Sousse, Tunisia, LNCS, volume 14064, Springer, pages 417-441, July, 2023 [Bibtex]
- J. Hu, W. Wang, K. Gaj, L. Wang, and H. Wang, Engineering practical rank-code-based cryptographic schemes on embedded hardware. A case study on ROLLO, IEEE Transactions on Computers, volume 72, number 7, pages 2094-2110, July, 2023 [Bibtex]
- V.B. Dang, K. Mohajerani, and K. Gaj, High-speed hardware architectures and FPGA benchmarking of CRYSTALS-Kyber, NTRU, and Saber, IEEE Transactions on Computers, volume 72, number 2, pages 306-320, Feb, 2023 [Bibtex]
- L. Beckwith, D.T. Nguyen, and K. Gaj, High-performance hardware implementation of CRYSTALS-Dilithium, 20th International Conference on Field-Programmable Technology, FPT 2021, IEEE, 12, 2021 [Bibtex]
- A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj, A lightweight implementation of Saber resistant against side-channel attacks, 22nd International Conference on Cryptology in India, Indocrypt 2021, Dec, 2021 [Bibtex]
- D.T. Nguyen and K. Gaj, Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists, 12th International Conference on Post-Quantum Cryptography, PQCrypto 2021, LNCS, volume 12841, pages 234-254, July, 2021 [Bibtex]
- A. Abdulgadir, S. Lin, F. Farahmand, J.-P. Kaps, and K. Gaj, Side-channel resistant implementations of a novel lightweight authenticated cipher with application to hardware security, Proc. Great Lakes Symposium on VLSI, GLSVLSI 2021, pages 229-234, June, 2021 [Bibtex]
- K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Hardware benchmarking of Round 2 candidates in the NIST lightweight cryptography standardization process, 24th Design, Automation and Test in Europe Conference, DATE 2021, Feb, 2021 [Bibtex]
- M. Andrzejczak and K. Gaj, A multiplatform parallel approach for lattice sieving algorithms, International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2020, LNCS, volume 12452, pages 661-680, 2020 [Bibtex]
- J. Xie, K. Basu, K. Gaj, and U. Guin, Special session: The recent advance in hardware implementation of post-quantum cryptography, IEEE VLSI Test Symposium 2020 (Virtual Conference), Apr., 2020 [Bibtex]
- M.X. Lyons and K. Gaj, Sampling from discrete distributions in combinational hardware with application to post-quantum cryptography, Design, Automation and Test in Europe Virtual Conference and Exhibition, DATE 2020, Apr, 2020 [Bibtex]
- D.T. Nguyen, V.B. Dang, and K. Gaj, High-level synthesis in implementing and benchmarking number theoretic transform in lattice-based post-quantum cryptography using software/hardware codesign, 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, pages 247-257, April, 2020 [Bibtex]