Post-Quantum Cryptography in Hardware and Embedded Systems

Post-Quantum Cryptography

Major investments by national governments and high-tech companies have led to the first demonstrations of quantum supremacy, i.e., computations conducted by a quantum computer that no classical computer can perform in any feasible amount of time. The goal of this project is to support NIST and other standardization organizations in their efforts to develop a new generation of public-key cryptographic standards resistant to quantum computers. The desired features of these algorithms, collectively known as post-quantum cryptography (PQC), are that they can be implemented using traditional software and hardware but are resistant to all known attacks using both quantum and classical computers. We aim to set the foundation for the early, systematic, and comprehensive study of the hardware and embedded system efficiency and security of the algorithms already selected for standardization and the remaining candidates, such as the Round 2 Additional Digital Signature Schemes. The next 5-10 years are very likely to bring the biggest revolution in cryptography since the invention of public-key cryptography in the mid-1970s. This project has given us a unique opportunity to influence the choice of future cryptographic standards, which will likely be deployed within the next decade and remain in use for a significant portion (if not the rest) of the 21st century.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.

Latest News:

Ayomikun Akindahunsi defended his MS Thesis

Ayomikun A. Akindahunsi defended his Master's Thesis, titled "Efficient Implementation of the BFV Fully Homomorphic Encryption Scheme on Google TPUs," on July 29, 2026. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh. (07/30/2026)

Kowsyap Pranay Kumar Musumuri defended his MS Thesis

Kowsyap Pranay Kumar Musumuri defended his Master's Thesis, titled "Reconfigurable High-Speed Hardware Accelerator for the MAYO Post-Quantum Signature Scheme," on July 29, 2026. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Pudukotai Dinakarrao. (07/30/2026)

GMU visit by Dr Xie and Dr Basu Roy

Visit of Dr. Jiafeng (Harvest) Xie and Dr. Debapriya Basu Roy

On July 27, 2026, at the invitation of Dr. Gaj, the following two well-known researchers in the area of efficient and secure implementations of Post-Quantum Cryptography visited GMU: Dr. Jiafeng (Harvest) Xie, Associate Professor in the Department of Electrical and Computer Engineering at Villanova University, and Dr. Debapriya Basu Roy, Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Kanpur. Dr. Xie gave a seminar titled "Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation and Architectural Innovation," followed by the talk by Dr. Basu Roy, titled "Hardware Implementation of a Stealthy and Lightweight Backdoor for CRYSTALS-Kyber in Hybrid Cryptosystems." The event included lunch attended by Dr. Xie, Dr. Basu Roy, Dr. Khasawneh, Dr. Zhang, and Dr. Gaj. On the right is a photo of Dr. Gaj with the visitors. (07/28/2026)

Trip to the National Cryptologic Museum

On May 29, 2026, Dr. Gaj, Dr. Mark, and Mohammadreza Fasihi (President of the GMU IEEE Student Branch) organized a trip to the National Cryptologic Museum, located near the headquarters of the National Security Agency in Fort Meade, MD. The event was intended as a team-building and social event for members of the Center for Trusted, Accelerated, and Secure Computing and Communication (C-TASC) and the IEEE Student Branch at GMU. It included the guided tour of the museum and the group lunch in the nearby bakery. The event was attended by about 20 GMU participants. (05/30/2026)

Luke Beckwith received the Outstanding Academic Achievement Award

During the ECE Departmental Awards Ceremony held on May 15, 2026, Luke Beckwith received the Outstanding Academic Achievement Award for the PhD in Electrical and Computer Engineering, granted to those students who have completed an outstanding PhD thesis and contributed to their field through excellence in research. (05/16/2026)

Luke Beckwith defended his Ph.D. Thesis

Luke Beckwith defended his Ph.D. Thesis, titled "Efficient and Secure Implementation of Post-Quantum Cryptography," on April 30, 2026. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh, and Dr. Zhang. (05/01/2026)

Luke Beckwith defended his Ph.D. Thesis Proposal

Luke Beckwith defended his Ph.D. Thesis Proposal, titled "Efficient and Secure Implementation of Post-Quantum Cryptography," on December 16, 2025. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh, and Dr. Zhang. (12/17/2025)

Kamyar Mohajerani defended his Ph.D. Thesis

Kamyar Mohajerani defended his Ph.D. Thesis, titled "Efficient and Secure Hardware Implementation of Cryptographic Algorithms," on July 31, 2025. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Manoj PD, and Dr. Zhang. (08/01/2025)

Dr. Gaj serves as a member of the Program Committees for LightSEC 2025, OPTIMIST 2025, DATE 2026, and CHES 2026

Dr. Gaj serves as a member of the Program Committees for the following conferences and workshops:

Multiple student members of CERG are contributing their time and expertise, serving as sub-reviewers for these conferences and workshops. (07/22/2025)

Dr. Gaj gave a seminar at the Polish National Institute of Telecommunications

On June 27, 2025, Dr. Gaj gave a hybrid seminar, titled "Basic Features and Hardware Implementations of Post-Quantum Cryptography Digital Signature Schemes," at the Polish National Institute of Telecommunications (NIT) in Warsaw, Poland. The seminar was hosted by Dr. Elzbieta Andrukiewicz, Head of IT Security Evaluation Facility (ITSEF) at NIT. The talk was based on the joint work with Luke Beckwith, Robert Wallace, and Kowsyap Pranay Kumar Musumuri. The seminar was attended by the representatives of academia, governmental agencies, and trust service providers in Poland. (06/28/2025)

Dr. Gaj spoke at CryptArchi 2025

Dr. Gaj gave a talk titled "Hardware Implementations of Post-Quantum Cryptography Digital Signature Schemes," at the 20th CryptArchi Workshop on Cryptographic Architectures Embedded in Logic Devices, held on June 15-18, 2025, in Autrans en Vercors, Grenoble, France. This talk was based on the joint work with Luke Beckwith, Robert Wallace, and Kowsyap Pranay Kumar Musumuri. (06/19/2025)

Luke Beckwith gave a talk at CBCrypto 2025

Luke Beckwith gave a talk titled "Towards Hardware Acceleration of LESS with Canonical Forms" at the International Workshop on Code-Based Cryptography, CBCrypto 2025, held in Madrid, Spain, on May 3-4, 2025. (05/05/2025)

Dr. Gaj spoke at FIPS 'n' Chips Crypto Module Bootcamp

Dr. Gaj will gave a talk titled "Implementing PQC in Hardware: Challenges and Rewards," at the FIPS 'n' Chips Crypto Module Bootcamp, organized by atsec information security, held at the University of Texas at Austin, on March 25, 2025. The full list of speakers and panelists of this event is available here. (03/26/2025)

Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • L. Beckwith and K. Gaj, Hardware acceleration of the LESS canonical form computation, Cryptography and Communications, pages 1–20, Jan., 2026 [Bibtex]
  • E. Ferrufino, L. Beckwith, A. Abdulgadir, and J.-P. Kaps, FOBOS 3: An open-source platform for side-channel analysis and benchmarking, Journal of Cryptographic Engineering, volume 15, number 10, 2025 [pdf] [Bibtex]
  • L. Beckwith, H. Zhou, J.-P. Kaps, and K. Gaj, Power side-channel key recovery attack on a hardware implementation of BIKE, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Kobe, Japan, Dec., 2024 [Bibtex]
  • L. Beckwith, D.T. Nguyen, and K. Gaj, Hardware accelerators for digital signature algorithms Dilithium and FALCON, IEEE Design and Test, volume 41, number 5, pages 27–35, Oct., 2024 [Bibtex]
  • K. Mohajerani, L. Beckwith, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Lightweight champions of the world: Side-channel resistant open hardware for finalists in the NIST lightweight cryptography standardization process, ACM Transactions on Embedded Computing Systems, Jul., 2024 [Bibtex]
  • J. Hu, W. Wang, K. Gaj, D. Chen, and H. Wang, Universal Gaussian elimination hardware for cryptographic purposes, Journal of Cryptographic Engineering, volume 14, pages 383-397, May, 2024 [Bibtex]
  • E. Ferrufino, L. Beckwith, A. Abdulgadir, and J.-P. Kaps, FOBOS 3: An open-source platform for side-channel analysis and benchmarking, Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security (ASHES), Association for Computing Machinery, Copenhagen, Denmark, pages 5–14, Nov, 2023 [pdf] [Bibtex]
  • L. Beckwith, R. Wallace, K. Mohajerani, and K. Gaj, A high-performance hardware implementation of the LESS digital signature scheme, 14th International Conference on Post-Quantum Cryptography, PQCrypto 2023, College Park, MD, LNCS, volume 14154, Springer, pages 57-90, August, 2023 [Bibtex]
  • D.T. Nguyen and G. Kris, Fast Falcon signature generation and verification using ARMv8 NEON instructions, 14th International Conference on Cryptology, AFRICACRYPT 2023, Sousse, Tunisia, LNCS, volume 14064, Springer, pages 417-441, July, 2023 [Bibtex]
  • J. Hu, W. Wang, K. Gaj, L. Wang, and H. Wang, Engineering practical rank-code-based cryptographic schemes on embedded hardware. A case study on ROLLO, IEEE Transactions on Computers, volume 72, number 7, pages 2094-2110, July, 2023 [Bibtex]
  • V.B. Dang, K. Mohajerani, and K. Gaj, High-speed hardware architectures and FPGA benchmarking of CRYSTALS-Kyber, NTRU, and Saber, IEEE Transactions on Computers, volume 72, number 2, pages 306-320, Feb, 2023 [Bibtex]
  • A. Abdulgadir, J.-P. Kaps, and A. Salman, Enhancing information security courses with remotely accessible side-channel analysis setup, Proceedings of the 2022 on Great Lakes Symposium on VLSI, ACM, Irvine, CA, Jun, 2022 [pdf] [Bibtex]
  • L. Beckwith, D.T. Nguyen, and K. Gaj, High-performance hardware implementation of CRYSTALS-Dilithium, 20th International Conference on Field-Programmable Technology, FPT 2021, IEEE, 12, 2021 [Bibtex]
  • A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj, A lightweight implementation of Saber resistant against side-channel attacks, 22nd International Conference on Cryptology in India, Indocrypt 2021, Dec, 2021 [Bibtex]
  • D.T. Nguyen and K. Gaj, Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists, 12th International Conference on Post-Quantum Cryptography, PQCrypto 2021, LNCS, volume 12841, pages 234-254, July, 2021 [Bibtex]
  • A. Abdulgadir, S. Lin, F. Farahmand, J.-P. Kaps, and K. Gaj, Side-channel resistant implementations of a novel lightweight authenticated cipher with application to hardware security, Proc. Great Lakes Symposium on VLSI, GLSVLSI 2021, pages 229-234, June, 2021 [Bibtex]
  • K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Hardware benchmarking of Round 2 candidates in the NIST lightweight cryptography standardization process, 24th Design, Automation and Test in Europe Conference, DATE 2021, Feb, 2021 [Bibtex]
  • M. Andrzejczak and K. Gaj, A multiplatform parallel approach for lattice sieving algorithms, International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2020, LNCS, volume 12452, pages 661-680, 2020 [Bibtex]
  • J. Bahrami, V. Dang, A. Abdulgadir, K.N. Khasawneh, J.-P. Kaps, and K. Gaj, Lightweight implementation of the LowMC block cipher protected against side-channel attacks, Proc. 4th ACM Workshop on Attacks and Solutions in Hardware Security, ASHES 2020, pages 45-56, Nov, 2020 [pdf] [Bibtex]
  • J. Xie, K. Basu, K. Gaj, and U. Guin, Special session: The recent advance in hardware implementation of post-quantum cryptography, IEEE VLSI Test Symposium 2020 (Virtual Conference), Apr., 2020 [Bibtex]
  • M.X. Lyons and K. Gaj, Sampling from discrete distributions in combinational hardware with application to post-quantum cryptography, Design, Automation and Test in Europe Virtual Conference and Exhibition, DATE 2020, Apr, 2020 [Bibtex]
  • D.T. Nguyen, V.B. Dang, and K. Gaj, High-level synthesis in implementing and benchmarking number theoretic transform in lattice-based post-quantum cryptography using software/hardware codesign, 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, pages 247-257, April, 2020 [Bibtex]