CERG Research Areas

The research conducted at CERG can be split into four broad categories as shown below. Click on each link to download the pdf of a short presentation of past and current work of our group in these areas. Warning: the file size of the presentations is rather large.

Hardware Architectures for Cryptography and Cryptanalysis Side-Channel Attacks and Countermeasures, IP Protection
Efficient Software Implementation of Cryptologic Algorithms Low-Power Cryptography for RFID and Wireless Sensor Networks

Recent Publications by Research Area

Hardware Architectures for Cryptography and Cryptanalysis

AES & AES Candidates

  • K. Gaj and P. Chodowiec, Comparison of the hardware performance of the AES candidates using reconfigurable hardware, Proc. 3rd Advanced Encryption Standard Conference, pages pp. 40-54, April, 2000 [pdf] [Bibtex]
  • K. Gaj and P. Chodowiec, Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays, LNCS 2020, Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA Conference 2001 - Cryptographers' Track, pages 84-99, Apr., 2001 [pdf] [Bibtex]
  • P. Chodowiec, K. Gaj, P. Bellows, and B. Schott, Experimental testing of the Gigabit IPSec-compliant implementations of Rijndael and Triple DES using SLAAC-1V FPGA accelerator board, 4th International Information Security Conference, ISC 2001, Malaga, Spain, LNCS, volume 2200, pages 220–234, Oct., 2001 [pdf] [Bibtex]

eSTREAM Candidates

  • K. Gaj, G. Southern, and R. Bachimanchi, Comparison of hardware performance of selected phase 2 eSTREAM candidates, State of the Art of Stream Ciphers, SASC 2007, Bochum, Germany, Jan-Feb, 2007 [pdf] [Bibtex]
  • D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj, Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates, State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pages 151–162, Feb, 2008 [pdf] [Bibtex]

Hash-functions

  • T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, J. Flidr, T. Lehman, and B. Schott, Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512, Information Security, 5th International Conference, ISC 2002, Lecture Notes in Computer Science (LNCS), volume 2433, Springer-Verlag, pages 75–89, 2002 [pdf] [Bibtex]
  • R. Lien, T. Grembowski, and K. Gaj, A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512, RSA Conference, Cryptographer's Track, CT-RSA 2004, San Francisco, CA, LNCS, volume 2964, pages 324–328, Feb., 2004 [pdf] [Bibtex]

Montgomery Multipliers

  • M. Huang, K. Gaj, S. Kwon, and T. El-Ghazawi, An optimized hardware architecture for the Montgomery Multiplication Algorithm, PKC 2008: 11th International Workshop on Practice and Theory in Public Key Cryptography, Barcelona, Spain, pages 214-228, March, 2008 [pdf] [Bibtex]

ECC Cryptosystems

  • N. Nguyen, K. Gaj, D. Caliga, and T. El-Ghazawi, Implementation of elliptic curve cryptosystems on a reconfigurable computer, IEEE International Conference on Field-Programmable Technology, FPT 2003, Tokyo, Japan, Dec. 2003, pages 60–67, 2003 [pdf] [Bibtex]
  • S. Bajracharya, C. Shu, K. Gaj, and T. El-Ghazawi, Implementation of elliptic curve cryptosystems over GF(2^n) in optimal normal basis on a reconfigurable computer, 14th International Conference on Field Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, pages 1001-1005, Aug, 2004 [pdf] [Bibtex]

Pairing-based Cryptosystems

Hardware Architectures for Cryptanalysis

  • S. Bajracharya, D. Misra, K. Gaj, and T. El-Ghazawi, Reconfigurable hardware implementation of mesh routing in number field sieve factorization, Proc. IEEE 2004 Conference on Field Programmable Technology, FPT 2004, Brisbane, Australia, Dec. 6-8, 2004, pages 263–270, 2004 [pdf] [Bibtex]
  • K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M. Khaleeluddin, and R. Bachimanchi, Implementing the elliptic curve method of factoring in reconfigurable hardware, Cryptographic Hardware and Embedded Systems – CHES 2006, Lecture Notes in Computer Science (LNCS), volume 4249, Springer , Berlin / Heidelberg, pages 119–133, Oct, 2006 [php] [Bibtex]
  • G. Southern, C. Mason, L. Chikkam, P. Baier, and K. Gaj, FPGA implementation of high throughput circuit for trial division by small primes, SHARCS 2007: Special-purpose Hardware for Attacking Cryptographic Systems, SHARCS, pages 3-21, Sep, 2007 [pdf] [Bibtex]

Side-Channel Attacks and Countermeasures, IP Protection

  • I. Verbauwhede, K. Tiri, D. Hwang, and P. Schaumont, Circuits and design techniques for secure ICs resistant to side-channel attacks, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT '06), May, 2006 [Bibtex]
  • D. Hwang, K. Tiri, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks, IEEE Journal of Solid-State Circuits, volume 41, number 4, pages 781–792, Apr, 2006 [Bibtex]
  • D. Hwang, P. Schaumont, K. Tiri, and I. Verbauwhede, Securing embedded systems, IEEE Security & Privacy Magazine, volume 4, number 2, pages 40-49, Mar, 2006 [Bibtex]
  • K. Tiri, D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, Prototype IC with WDDL and differential routing – DPA resistance assessment, Cryptographic Hardware and Embedded Systems – CHES 2005, Lecture Notes in Computer Science (LNCS), volume 3659, Springer, pages 354–365, 2005 [Bibtex]
  • K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, A side-channel leakage free coprocessor IC in 0.18μm CMOS for embedded AES-based cryptographic and biometric processing, 42nd Design Automation Conference, pages 222–227, 2005 [Bibtex]

Efficient Software Implementation of Cryptologic Algorithms

Comparison of Public Domain Multi-precision Libraries

  • A. Abusharekh and K. Gaj, Comparative analysis of software libraries for public key cryptography, Software Performance Enhancement for Encryption and Decryption, SPEED 2007, Amsterdam, the Netherlands, pages 3–19, June, 2007 [pdf] [Bibtex]

Pairing-based cryptosystems

Cryptography on Reconfigurable Computers

  • A. Staicu, J. Radzikowski, K. Gaj, N. Alexandridis, and T. El-Ghazawi, Implementation trade-offs of triple DES in the SRC-6e reconfigurable computing environment, Proc. 2001 MAPLD International Conference, Sep., 2001 [pdf] [Bibtex]
  • N. Nguyen, K. Gaj, D. Caliga, and T. El-Ghazawi, Implementation of elliptic curve cryptosystems on a reconfigurable computer, IEEE International Conference on Field-Programmable Technology, FPT 2003, Tokyo, Japan, Dec. 2003, pages 60–67, 2003 [pdf] [Bibtex]
  • S. Bajracharya, D. Misra, K. Gaj, and T. El-Ghazawi, Reconfigurable hardware implementation of mesh routing in number field sieve factorization, Proc. IEEE 2004 Conference on Field Programmable Technology, FPT 2004, Brisbane, Australia, Dec. 6-8, 2004, pages 263–270, 2004 [pdf] [Bibtex]
  • S. Bajracharya, C. Shu, K. Gaj, and T. El-Ghazawi, Implementation of elliptic curve cryptosystems over GF(2^n) in optimal normal basis on a reconfigurable computer, 14th International Conference on Field Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, pages 1001-1005, Aug, 2004 [pdf] [Bibtex]
  • T. El-Ghazawi, E. El-Araby, M. Huang, K. Gaj, V. Kindratenko, and D. Buell, The promise of high-performance reconfigurable computing, Computer, volume 41, number 2, pages 69-76, Feb, 2008 [Bibtex]
  • P. Saha, E. El-Araby, M. Huang, M. Taher, S. Lopez-Buedo, T. El-Ghazawi, C. Shu, K. Gaj, A. Michalski, and D. Buell, Portable library development for reconfigurable computing systems: A case study, Elsevier Parallel Computing: Systems & Applications, volume 34, number 4+5, pages 245–260, May, 2008 [Bibtex]

Low-Power Cryptography for RFID and Wireless Sensor Networks

  • J.-P. Kaps, Chai-tea, cryptographic hardware implementations of xTEA, Progress in Cryptology – INDOCRYPT 2008, Lecture Notes in Computer Science (LNCS), volume 5365, Springer, Heidelberg, pages 363–375, Dec, 2008 [extended version, pdf] [Bibtex]
  • J.-P. Kaps, G. Gaubatz, and B. Sunar, Cryptography on a speck of dust, Computer, volume 40, number 2, pages 38–44, Feb, 2007 [Pre-print, pdf] [Bibtex]
  • J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing, Embedded and Ubiquitous Computing (EUC-06) Workshop Proceedings, Lecture Notes in Computer Science (LNCS), volume 4097, Springer, pages 372–381, Aug, 2006 [expanded version, pdf] [Bibtex]
  • J.-P. Kaps, Cryptography for ultra-low power devices, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 2006, Ph.D. Dissertation [pdf] [Bibtex]
  • J.-P. Kaps, K. Yüksel, and B. Sunar, Energy scalable universal hashing, IEEE Transactions on Computers, volume 54, number 12, pages 1484–1495, Dec, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, E. Öztürk, and B. Sunar, State of the art in ultra-low power public key cryptography for wireless sensor networks, Third IEEE International Conference on Pervasive Computing and Communications Workshops, Workshop on Pervasive Computing and Communications Security–PerSec'05, IEEE Computer Society, pages 146–150, Mar, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, and B. Sunar, Public key cryptography in sensor networks—revisited, 1st European Workshop on Security in Ad-Hoc and Sensor Networks (ESAS 2004), Lecture Notes in Computer Science (LNCS), volume 3313, Springer, Heidelberg, pages 2–18, August, 2004 [pdf] [Bibtex]
  • K. Yüksel, J.-P. Kaps, and B. Sunar, Universal hash functions for emerging ultra-low-power networks, Proceeding of The Communications Networks and Distributed Systems Modeling and Simulation Conference (CNDS), Society for Modeling and Simulation International (SCS), San Diego, CA, January, 2004 [pdf] [Bibtex]