CERG Seminars are held in the Engineering Building on the GMU Fairfax campus unless noted otherwise. Parking is available in the Sandy Creek parking deck near the Engineering Building. Directions to the campus can be found here. The seminar talks are usually 45 to 60 minutes long and are open to the public. If you wish to be notified about future seminars, please send an e-mail to Jens-Peter Kaps.

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Crypto Night

ECE 646 Cryptography and Computer Network Security, Project Presentations Date: Friday, December 9th, 4:30 PM - 9:00 PM
Location: Engineering Building, Room 4201

Join us for an evening of exciting presentations by ECE 646 students. The exact schedule is posted here. We have 4 sessions:

  1. 4:30 PM -- Security of Cloud Services
  2. 5:45 PM -- Attacks against Cryptosystems
  3. 6:50 PM -- Authenticated Encryption
  4. 8:10 PM -- Device Security

Sources of Randomness in Digital Devices and Their Testability

Dr. Viktor Fischer, Hubert Curien Laboratory, Jean Monnet University, Saint-Etienne, France
Date: Wednesday, May 4th, 10:30 AM - 11:30 AM
Location: Engineering Building, Room 4801

Digital electronic devices are often used to implement data security systems-on-chip (SoC), like smart cards. Random bit stream generators constitute one of the main building blocks of such systems. They use some uncontrollable physical analog phenomenon as a source of randomness. The random variations in this analog process must be converted to a digital bitstream using some intrinsic analog to digital conversion or some extrinsic digitization technique. This conversion should be feasible using purely digital technology, because the use of some analog electronic blocks inside the device would increase the total cost of the system. (Full Announcement)

PUF designed with Resistive RAM and Ternary States

Dr. Bertrand Cambou, School of Informatics, Computing, and Cyber-Systems, Northern Arizona University
Date: Monday, April 4th, 3:15 PM - 4:15 PM
Location: Engineering Building, Room 3507

The designs of Physically Unclonable Functions (PUFs) described in this presentation are based on Resistive RAMs incorporating ternary states with the objective to reduce false negative authentications (FNA) with low Challenge-Response-Pair (CRP) error rates. Unlike other error correction method, the method is not increasing false positive authentications (FPA). The ternary states, the "Xs", allow the blanking of all cells that are not characterized as consistently capable to generate stable and easy to read "1s" or "0s" PUF challenges. Experimental data extracted from Cu/TaOx/Pt Resistive RAM samples confirms that such a method can generate CRPs having error rates below 8 ppm useable for secure hardware authentication. Random Number Generators (RNG) can also be enhanced by the same ternary architecture. (Full Announcement)