Rabia Shahid

Contact

3100 Engineering Building
George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
 Office: Engineering Building, Room 3231
Phone (lab): 703-993-1561
E-Mail: rshahid'at'gmu.edu
Curriculum Vitae: PDF

Research Interests

  • Cryptographic Hardware and Embedded Systems
  • Pairing based Cryptography
  • High Performance Parallel Computing
  • Reconfigurable Computing
  • Microprocessor Development

Advisor: Dr. Kris Gaj

Biography

Rabia graduated from George Mason University with the Ph.D. degree in Electrical and Computer Engineering in Summer 2017. She received her M.S. degree in Computer Engineering from GWU in 2009 and B.S. degree from COMSATS Islamabad, Pakistan in 2007.

Publications

  • T. Winograd, R. Shahid, and K. Gaj, An automated scheduler-based approach for the development of cryptoprocessors for pairing-based cryptosystems, 26th Reconfigurable Architectures Workshop, RAW 2019, Rio de Janeiro, Brazil, May, 2019 [Bibtex]
  • R. Shahid, T. Winograd, and K. Gaj, A generic approach to the development of coprocessors for Elliptic Curve Cryptosystems, 24th Reconfigurable Architectures Workshop, RAW 2017, Orlando, FL, May, 2017 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Jun., 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex]
  • R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of five round three SHA-3 candidates, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]