3100 Engineering Building
George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
Office: Engineering Building, Room 3224|
Phone (lab): 703-993-1561
- Glitch Analysis for FPGA based secure circuits.
- FPGA based Embedded system.
- Design and Analysis of secure Hash algorithms.
Advisor: Dr. Jens-Peter Kaps
She worked towards her M.S. degree in Computer Engineering at GMU. She joined CERG group in spring 2010. She received her B.S. degree in Electronics & Communication from Gujarat University, India. She has implemented Keccak Hash function (SHA-3 round 2 candidate) for maximum throughput to area ratio. She has experience designing PCB layout for Electronic Power Conditioning systems at ISRO (Indian Space Research Organization).
- K. Shah, An innovative approach to detect glitches in hardware implementations on FPGAs, ECE Department, George Mason University, Fairfax, Virginia, USA, Feb, 2013, Master's Thesis [Bibtex]