Post-Quantum Cryptography in Hardware and Embedded Systems

Post-Quantum Cryptography

Major investments by national governments and high-tech companies have led to first demonstrations of quantum supremacy, i.e., computations conducted by a quantum computer that no classical computer can perform in any feasible amount of time. The goal of this project is to support NIST in its effort to develop a new generation of public-key cryptographic standards, resistant against quantum computers, a.k.a. NIST Post-Quantum Cryptography (PQC) Standardization Process. In Rounds 1 and 2 of this effort, the assessment of PQC candidates has focused primarily on their security and software efficiency. Our aim is to set the foundation for the early, systematic, and comprehensive study of the hardware and embedded system efficiency of the most promising PQC candidates. The next 5-10 years are very likely to bring the biggest revolution in cryptography, since the invention of public-key cryptography in mid-1970s. This project gives us a unique opportunity to influence the choice of future cryptographic standards, which are likely to be developed and deployed within the next decade and remain in use for the significant portion (if not the rest) of the 21st century.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Job Announcements:

GRA Positions in Post-Quantum Cryptography

CERG is seeking qualified candidates for multiple Graduate Research Assistant positions in the area of efficient implementations of Post-Quantum Cryptosystems, side-channel attacks targeting these cryptosystems, and countermeasures against such attacks. The desired qualifications include strong mathematical background in algebra and number theory, experience in hardware design using hardware description languages, and knowledge of C and scripting languages, such as Python. Additional experience in Magma or SageMath, ASIC or FPGA design, software/hardware codesign, High-Level Synthesis, embedded software development, and Linux operating system is a plus.

GRA Position in Lightweight Cryptography

CERG is seeking qualified candidates for a Graduate Research Assistant position in the area of efficient and secure implementations of Lightweight Cryptography. The desired qualifications include experience in embedded systems, knowledge of C, assembly and scripting languages, hardware design using hardware description languages, Linux operating system, and strong experimental skills. Additional experience in side-channel and fault attacks, countermeasures against these attacks, ASIC or FPGA design, software/hardware codesign, embedded software development, and/or circuit/PCB design is a plus.

All positions are open starting in August 2023 or January 2024. Qualified candidates should apply to the ECE PhD program at George Mason University, indicating Dr. Gaj and/or Dr. Kaps as possible future advisors. In parallel, an earlier e-mail contact with Dr. Gaj and/or Dr. Kaps is highly recommended.


Latest News:

CERG paper accepted for presentation at AfricaCrypt 2023

The paper co-authored by Duc T. Nguyen and Kris Gaj, titled "Fast Falcon Signature Generation and Verification Using ARMv8 NEON Instructions" has been accepted for presentation at the 14th International Conference on Cryptology, AfricaCrypt 2023, to be held in Sousse, Tunisia, on July 19-21, 2023. (05/06/2023)


Dr. Gaj scheduled to speak at CryptArchi 2023

Dr. Gaj is scheduled to give a talk titled "High-Speed Hardware Implementations of Post-Quantum Cryptography Digital Signature Schemes" at the 19th CryptArchi Workshop on Cryptographic Architectures Embedded in Logic Devices, to be held on June 11-14, 2023, in Castro Urdiales, Cantabria, Spain. This talk will be based on the joint work with Luke Beckwith, Robert Wallace, Duc T. Nguyen, and Kamyar Mohajerani. (05/06/2023)


Dr. Gaj scheduled to speak at an FCCM 2023 Workshop

Dr. Gaj is scheduled to give a talk titled "Toward Protecting Hardware Implementations of Lattice-Based Cryptosystems Against Side-Channel Attacks" at the FCCM 2023 Workshop on Developing a Community-Driven Cloud-Based Infrastructure for Post-Quantum Cryptography Side-Channel Attack Analysis, to be held on May 8, 2023, in Marina Del Rey, CA. (05/06/2023)


Duc T. Nguyen defended his Ph.D. Thesis

Duc T. Nguyen defended his Ph.D. Thesis, titled "Accelerating Polynomial Multiplication for Post-Quantum Cryptography," on April 28, 2023. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh, and Dr. Gordon. (04/29/2023)


Dr. Gaj interviewed during GMU Quantum Week

Dr. Gaj participated in the Quantum Week held on April 13-14, 2023, at George Mason University. As a part of this event, Dr. Gaj was interviewed by Dr. Jamil Jaffer, the Founder and Executive Director of the GMU National Security Institute. The topic of this fireside chat was Post-Quantum Cryptography and Security. (04/15/2023)


CERG released its report on SCA evaluation and FPGA benchmarking of lightweight cryptography NIST finalists

On April 4, 2023, members of CERG released their report titled "SCA Evaluation and Benchmarking of Finalists in the NIST Lightweight Cryptography Standardization Process." The report was co-authored by Kamyar Mohajerani, Luke Beckwith, Abubakr Abdulgadir, Eduardo Ferrufino, Jens-Peter Kaps, and Kris Gaj. It summarized contributions by several Side-Channel Security Evaluation Labs as well as multiple developers of side-channel-protected hardware and software implementations from all over the world. The report was published as the Cryptology ePrint Archive Paper 2023/484 and was submitted for consideration by the NIST Lightweight Cryptography team. (04/05/2023)


Dr. Gaj served as a co-chair for the Hardware Security track at GLSVLSI 2023

Dr. Gaj served as a co-chair for the Hardware Security track at GLSVLSI 2023 to be held in Knoxville, TN, on June 5-7, 2023. The program of the conference includes 8 talks and 3 posters related to this track. (02/27/2023)


Dr. Gaj spoke at the VICEROY DECREE 1st Annual Symposium

Dr. Gaj participated in the VICEROY DECREE First Annual Symposium held online on February 9-10, 2023. He was a part of the panel debating on the topic "What are the main challenges to teach post quantum cryptography as part of mainstream undergraduate programs in US universities?" He also gave a master class seminar titled "PQC Standardization, As Driven by NIST, Summarized." (02/11/2023)


Viet Ba Dang defended his Ph.D. Thesis

Viet Ba Dang defended his Ph.D. Thesis, titled "Efficient and Secure Hardware Architectures and Software/Hardware Co-Designs for Post-Quantum Cryptography," on December 2, 2022. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Khasawneh, and Dr. Albanese. (12/03/2022)


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • A. Abdulgadir, J.-P. Kaps, and A. Salman, Enhancing information security courses with remotely accessible side-channel analysis setup, Proceedings of the 2022 on Great Lakes Symposium on VLSI, ACM, Irvine, CA, Jun, 2022 [Bibtex]
  • L. Beckwith, D.T. Nguyen, and K. Gaj, High-performance hardware implementation of CRYSTALS-Dilithium, 20th International Conference on Field-Programmable Technology, FPT 2021, IEEE, 12, 2021 [Bibtex]
  • A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj, A lightweight implementation of Saber resistant against side-channel attacks, 22nd International Conference on Cryptology in India, Indocrypt 2021, Dec, 2021 [Bibtex]
  • D.T. Nguyen and K. Gaj, Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists, 12th International Conference on Post-Quantum Cryptography, PQCrypto 2021, LNCS, volume 12841, pages 234-254, July, 2021 [Bibtex]
  • A. Abdulgadir, S. Lin, F. Farahmand, J.-P. Kaps, and K. Gaj, Side-channel resistant implementations of a novel lightweight authenticated cipher with application to hardware security, Proc. Great Lakes Symposium on VLSI, GLSVLSI 2021, pages 229-234, June, 2021 [Bibtex]
  • K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Hardware benchmarking of Round 2 candidates in the NIST lightweight cryptography standardization process, 24th Design, Automation and Test in Europe Conference, DATE 2021, Feb, 2021 [Bibtex]
  • M. Andrzejczak and K. Gaj, A multiplatform parallel approach for lattice sieving algorithms, International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2020, LNCS, volume 12452, pages 661-680, 2020 [Bibtex]
  • J. Bahrami, V. Dang, A. Abdulgadir, K.N. Khasawneh, J.-P. Kaps, and K. Gaj, Lightweight implementation of the lowmc block cipher protected against side-channel attacks, Proc. 4th ACM Workshop on Attacks and Solutions in Hardware Security, ASHES 2020, pages 45-56, Nov, 2020 [pdf] [Bibtex]
  • J. Xie, K. Basu, K. Gaj, and U. Guin, Special session: The recent advance in hardware implementation of post-quantum cryptography, IEEE VLSI Test Symposium 2020 (Virtual Conference), Apr., 2020 [Bibtex]
  • M.X. Lyons and K. Gaj, Sampling from discrete distributions in combinational hardware with application to post-quantum cryptography, Design, Automation and Test in Europe Virtual Conference and Exhibition, DATE 2020, Apr, 2020 [Bibtex]
  • D.T. Nguyen, V.B. Dang, and K. Gaj, High-level synthesis in implementing and benchmarking number theoretic transform in lattice-based post-quantum cryptography using software/hardware codesign, 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, pages 247-257, April, 2020 [Bibtex]
  • A. Abdulgadir, W. Diehl, and J.-P. Kaps, An open-source platform for evaluation of hardware implementations of lightweight authenticated ciphers, 2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, Dec., 2019 [Accepted Version, pdf] [Bibtex]
  • M. Andrzejczak, F. Farahmand, and K. Gaj, Full hardware implementation of the post-quantum public-key cryptography scheme Round5, 2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, Dec., 2019 [Bibtex]
  • V.B. Dang, F. Farahmand, M. Andrzejczak, and K. Gaj, Implementing and benchmarking three lattice-based post-quantum cryptography algorithms using software/hardware codesign, 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, pages 206-214, Dec., 2019 [Bibtex]
  • D.T. Nguyen, V.B. Dang, and K. Gaj, A high-level synthesis approach to the software/hardware codesign of NTT-based post-quantum cryptography algorithms, 2019 International Conference on Field Programmable Technology, FPT 2019, Tianjin, China, pages 371-374, Dec., 2019 [Bibtex]
  • F. Farahmand, D.T. Nguyen, V.B. Dang, A. Ferozpuri, and K. Gaj, Software/hardware codesign of the post quantum cryptography algorithm NTRUEncrypt using high-level synthesis and register-transfer level design methodologies, 29th International Confererence on Field-Programmable Logic and Applications, FPL 2019, Barcelona, Spain, Sep., 2019 [Bibtex]
  • T. Winograd, R. Shahid, and K. Gaj, An automated scheduler-based approach for the development of cryptoprocessors for pairing-based cryptosystems, 26th Reconfigurable Architectures Workshop, RAW 2019, Rio de Janeiro, Brazil, May, 2019 [Bibtex]
  • F. Farahmand, V.B. Dang, D.T. Nguyen, and K. Gaj, Evaluating the potential for hardware acceleration of four NTRU-based Key Encapsulation Mechanisms using software/hardware codesign, 10th International Conference on Post-Quantum Cryptography, PQCrypto 2019, Chongqing, China, LNCS, Springer, May, 2019 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, Cryptology ePrint Archive, number 184, March, 2019 [Bibtex]
  • F. Farahmand, M.U. Sharif, K. Briggs, and K. Gaj, A high-speed constant-time hardware implementation of NTRUEncrypt SVES, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • A. Ferozpuri and K. Gaj, High-speed FPGA implementation of the NIST Round 1 Rainbow signature scheme, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • M. Tempelmeier, J.-P. Kaps, and G. Sigl, Experimental power and performance evaluation of CAESAR hardware finalists, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • G. Banegas, P.S.L.M. Barreto, B.O. Boidje, P.-L. Cayrel, G.N. Dione, K. Gaj, C.T. Gueye, R. Haeussler, J.B. Klamti, O. Ndiaye, D.T. Nguyen, and E. Persichetti, DAGS: Key encapsulation using Dyadic GS codes, Journal of Mathematical Cryptology, volume 12, number 4, pages 221–240, December, 2018 [Bibtex]
  • K. Gaj, Challenges and rewards of implementing and benchmarking Post-Quantum Cryptography in hardware, The 28th ACM Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, ACM, May, 2018 [Bibtex]
  • F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Improved lightweight implementations of CAESAR authenticated ciphers, The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, IEEE, pages 29–36, April, 2018 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, The CAESAR-api in the real world - towards a fair evaluation of hardware CAESAR candidates, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, April, 2018 [Bibtex]