Post-Quantum Cryptography in Hardware and Embedded Systems

Post-Quantum Cryptography

Major investment by companies, such as Google, IBM, Intel, Microsoft, and NTT, has led to the first general-purpose quantum processors, and selecting quantum computing as one of the ten breakthrough technologies of 2017. The goal of this project is to support NIST in its effort to develop a new generation of public-key cryptographic standards, resistant against quantum computers, a.k.a. NIST Post-Quantum Cryptography (PQC) Standardization Process. In Round 1 of this effort, the assessment of PQC candidates has focused primarily on their security and software efficiency. Relatively little progress has been made so far to understand the true potential of these algorithms for efficient and secure hardware and embedded systems implementations. The goal of this project is to set the foundation for the early, systematic, and comprehensive study of the hardware efficiency of the most promising PQC candidates, through the definition of the universal PQC Hardware API, generation of the universal Development Package, and employment of novel methodologies such as Software/Hardware Codesign and High-Level Synthesis. The next 5-10 years are very likely to bring the biggest revolution in cryptography, since the invention of public-key cryptography in mid-1970s. This project gives us a unique opportunity to influence the choice of future cryptographic standards, which are likely to be developed and deployed within the next decade and remain in use for the significant portion (if not the rest) of the 21st century.

Welcome to the webpage of the Cryptographic Engineering Research Group at George Mason University. Cryptography, from Greek krpto (hidden) and grapho (write), is the science and practice of hiding information. Most Internet users come in contact with cryptography when they go to a secure website of an Internet retailer. Other popular applications are secure e-mail, Internet banking, mobile phones, etc. Cryptography has its roots in mathematics, computer science and engineering. Cryptographic Engineering is concerned with all aspects of implementing cryptographic algorithms in hardware and / or software. This ranges from high performance implementations to ultra-low power implementations of public key and secret key algorithms, fault tolerant implementations, attack resistant implementation and even implementations of attacks.


Seminars:

Enabling a Control System Approach to Side-Channel and Fault Attacks

Ryan Matthew Carter, ECE MS Defense
Date: Wednesday, December 5th, 3:00 pm - 4:00 pm
Location: Engineering Building, Room 3507

As the number of embedded devices continues to grow, attacks that require physical access to the device become more plausible. Two sub-classifications of these attacks, Side-Channel Attacks (SCA) and Fault attacks, necessitate the attacker to be familiar with the target implementation. Side-Channel Attacks exploit information leaked by the target device to discover secret cryptographic keys. Fault attacks act upon the system to induce error in device operation that may result in information leakage or improper execution. The error produced by the attack is dependent on the method used to inject the fault. This paper discusses some of the advances in SCAs and Fault Attacks and proposes a control system approach to these classes of attacks. The result of the research is a System on a Chip (SOC) for measuring power consumption, analyzing results, and refining measurement as a feedback loop.


Job Announcements:

GRA Positions in Post-Quantum Cryptography

CERG is seeking qualified candidates for multiple Graduate Research Assistant positions in the area of efficient implementations of Post-Quantum Cryptosystems, side-channel attacks targeting these cryptosystems, and countermeasures against such attacks. The desired qualifications include strong mathematical background in algebra and number theory, experience in hardware design using hardware description languages, and knowledge of C and scripting languages, such as Python. Additional experience in Magma or SageMath, ASIC or FPGA design, software/hardware codesign, High-Level Synthesis, embedded software development, and Linux operating system is a plus.

GRA Position in Lightweight Cryptography

CERG is seeking qualified candidates for a Graduate Research Assistant position in the area of efficient and secure implementations of Lightweight Cryptography. The desired qualifications include experience in embedded systems, knowledge of C, assembly and scripting languages, hardware design using hardware description languages, Linux operating system, and strong experimental skills. Additional experience in side-channel and fault attacks, countermeasures against these attacks, ASIC or FPGA design, software/hardware codesign, embedded software development, and/or circuit/PCB design is a plus.

All positions are open starting in August 2019 or January 2020. Qualified candidates should apply to the ECE PhD program at George Mason University, indicating Dr. Gaj and/or Dr. Kaps as possible future advisors. In parallel, an earlier e-mail contact with Dr. Gaj and/or Dr. Kaps is highly recommended.


Latest News:

CERG paper accepted to PQCrypto 2019

The CERG paper entitled "Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign," co-authored by Farnoud Farahmand, Viet B. Dang, Duc Tri Nguyen, and Kris Gaj has been accepted for an oral presentation at the Tenth International Conference on Post-Quantum Cryptography, PQCrypto 2019, to be held at the Chongqing University, in Chongqing, China, on May 8-10, 2019. (01/13/2019)


Dr. Gaj gave presentations at FPT 2018

Dr. Gaj attended the 2018 International Conference on Field-Programmable Technology, FPT 2018, held in Naha, Okinawa, Japan, on December 10-14, 2018. Dr. Gaj gave an oral presentation entitled "A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES," based on the paper co-authored with Farnoud Farahmand, Malik Umar Sharif, and Kevin Briggs. He also gave a poster presentation, entitled "Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon," based on the paper co-authored with William Diehl, Farnoud Farahmand, Abubakr Abdulgadir, and Jens-Peter Kaps. After the main conference, Dr. Gaj attended the half-day workshop entitled "Embedded Machine Learning: Technology and Opportunities," organized by David Boland and Philip Leong from the University of Sydney in Australia. (12/15/2018)


Ahmed Ferozpuri gave a presentation at ReConFig 2018

Ahmed Ferozpuri attended the 2018 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, held in Cancun, Mexico, on December 3-5, 2018. He gave an oral presentation entitled "High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme," based on the paper co-authored with Kris Gaj. In the same session, Michael Tempelmeier from Technical University of Munich gave a talk entitled "Performance Evaluation of CAESAR Hardware Finalists," based on the paper co-authored with Jens-Peter Kaps from CERG, GMU and Georg Sigl from Technical University of Munich. (12/06/2018)


Matthew Ryan Carter defended his Master's Thesis

Matthew Ryan Carter defended his Master's Thesis entitled "Enabling a Control System Approach to Side-Channel and Fault Attacks," on December 5, 2018. Members of his Committee included: Dr. Kaps (Chair), Dr. Gaj, and Dr. Lorie. (12/06/2017)


Michael Lyons passed the Research Qualifying Exam

Michael Lyons passed the PhD Research Qualifying Exam (RQE) on December 3, 2018. As a part of the exam, he presented his paper entitled "Efficient Reduction Modulo 3 in FPGAs". The members of his RQE Committee included Dr. Gaj (Chair), Dr. Kaps, and Dr. Sasan. (12/04/2018)


Duc Nguyen earned the 4th place in the International Students' Olympiad in Cryptography NSUCRYPTO-2018

Duc Nguyen earned the 4th place in the International Students' Olympiad in Cryptography, NSUCRYPTO-2018, held on October 14-22, 2018. Duc participated in Round 2 for Professionals as a member of the team, including two of his colleagues from Ho Chi Minh City, Vietnam: Quan Doan and Quoc Bao Nguyen. The results of the competition were announced on December 3, 2018. That was Duc's third start in the Olympiad. His teams earned the third place in both 2016 and 2017. (12/04/2018)


Dr. Gaj and Dr. Kaps awarded NSF grant for research on Side-Channel Attack Countermeasures for Post-Quantum Cryptography

Dr. Gaj and Dr. Kaps were awarded a grant from the National Science Foundation for their project "SaTC: CORE: Medium: Collaborative: Countermeasures Against Side-Channels Attacks Targeting Hardware and Embedded System Implementations of Post-Quantum Cryptographic Algorithms". The period of performance is October 1, 2018 through September 30, 2022. The first year funding is $105,571, and the anticipated total funding $450,000. This project is a joint effort with the research groups of Dr. Reza Azarderakhsh and Dr. Mehrdad Nojoumian from Florida Atlantic University, and of Dr. Mehran Mozaffari Kermani from University of South Florida. GMU serves a lead organization for this effort. The total anticipated funding for all three universities is $1.2M. (09/08/2018)


Dr. Kaps and Dr. Gaj awarded NIST grant for research on Lightweight Cryptography

Dr. Kaps and Dr. Gaj were awarded a grant from the U.S. Department of Commerce (NIST) for their project "Lightweight Cryptography in Hardware and Embedded Systems". The period of performance is September 1, 2018 through August 31, 2021. The first year funding is $164,694, and the anticipated total funding $499,970. This project is a joint effort with the research group of Dr. William Diehl from Virginia Tech. (09/02/2018)


Dr. Gaj and Dr. Kaps awarded NIST grant for research on Post-Quantum Cryptography

Dr. Gaj and Dr. Kaps were awarded a grant from the U.S. Department of Commerce (NIST) for their project "Post-Quantum Cryptography in Hardware and Embedded Systems". The period of performance is September 1, 2018 through August 31, 2021. The first year funding is $161,918, and the anticipated total funding $500,000. (09/02/2018)


CERG becomes a part of CHEST

CERG has joined CHEST: Center for Hardware and Embedded Systems Security and Trust, developed as a part of the NSF Industry-University Cooperative Research Centers Program. CHEST, launched in May 2018, includes research groups from the following six universities: George Mason University, Northeastern University, the University of Cincinnati, the University of Connecticut, the University of Texas at Dallas, and the University of Virginia. The research activities of CHEST will cover security and trust at the following levels: systems/application, architectural and board, embedded-device, FPGA and ASIC, and circuit (including analog, RF, and digital). At GMU, the following research groups have become a part of CHEST: Accelerated, Secure, and Energy-Efficient Computing Lab (ASEEC), led by Dr. Homayoun; Green, Accelerated, and Trustworthy Engineering (GATE) Lab, led by Dr. Sasan, and Cryptographic Engineering Research Group (CERG), led by Drs. Gaj and Kaps. The planning meeting of CHEST took place on August 23-24, 2018, at George Mason University, with the participation of all collaborating universities, as well as representatives of National Science Foundation, Air Force Research Lab, and about 30 companies and industry/government labs. During the planning meeting Dr. Gaj gave the project proposal presentation entitled "Post-Quantum Cryptography in Hardware and Embedded Systems," and student members of CERG presented two posters about recent research activities of CERG. (2018/09/02)


Ahmed Ferozpuri passed the Research Qualifying Exam

Ahmed Ferozpuri passed the PhD Research Qualifying Exam (RQE) on August 31, 2018. As a part of the exam, he presented his paper entitled "High-Speed FPGA Implementation of the Rainbow Signature Scheme". The members of his RQE Committee included Dr. Gaj (Chair), Dr. Kaps, and Dr. Sasan. (2018/09/01)


Ted Winograd defended his PhD Thesis Proposal

Ted Winograd defended his PhD Thesis Proposal, entitled "A New Approach to the Development of Cryptographic Hardware Based on Specialized Computer-Aided Design Tools," on August 21, 2018. Members of his dissertation committee include Dr. Gaj (Chair), Dr. Homayoun (co-Chair), Dr. Kaps, and Dr. Ammann. (2018/08/22)


Dr. Gaj and Dr. Kaps gave presentations at CryptArchi 2018

Dr. Gaj and Dr. Kaps attended CryptArchi 2018, held in Guidel-Plages near Lorient, France, on June 17-20, 2018. Dr. Gaj gave a talk entitled "Post-Quantum Cryptography in Reconfigurable Hardware: Challenges, Opportunities, and State-of-the-Art ," and Dr. Kaps delivered a presentation entitled "Evaluation of DPA Protected Implementations of CAESAR Finalists ACORN and Ascon and other Candidates". (06/21/2018)


Dr. Gaj organized a special session and spoke at GLSVLSI 2018

Dr. Gaj attended the 28th ACM Great Lakes Symposium on VLSI - GLSVLSI 2018, held in Chicago, IL, on May 23-25, 2018. He served as an organizer of the special session on "Implementing and Benchmarking Post-Quantum Cryptography in Hardware," and gave a talk entitled "Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware". (05/26/2018)


Student members of CERG received special departmental awards

During the ECE Departmental Awards Ceremony held on May 17, 2018, several members of CERG were recognized with the following awards: William Diehl received the Outstanding Academic Achievement Award for Ph.D. students, Ahmad Salman, Rabia Shahid, Malik Umar Sharif, and Panasayya Yalla received Chairman's Awards, and Ahmed Ferozpuri received the Special Recognition Award. (05/18/2018)


Ahmed Ferozpuri spoke at ICMC 2018

Ahmed Ferozpuri spoke at the International Cryptographic Module Conference, held in Ottawa, Ontario, Canada, on May 8-11, 2018. He delivered an oral presentation entitled "Using FPGAs in the Cloud for Decentralized Trusted Execution". He also attended the pre-conference workshops, held on Tuesday, May 8. (05/11/2018)


Farnoud Farahmand spoke at FCCM 2018

Farnoud Farahmand spoke at the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, held in Boulder, CO, on April 29 - May 1, 2018. He delivered an oral presentation entitled "Improved Lightweight Implementations of CAESAR Authenticated Ciphers," co-authored with William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, and Kris Gaj. (05/02/2018)


William Diehl defended his PhD Thesis

William Diehl defended his PhD Thesis, entitled "Comparing Costs of Protecting Secret Key Ciphers Against Differential Power Analysis," on April 24, 2018. The members of his dissertation committee included Dr. Gaj (Chair), Dr. Kaps, Dr. Sasan, and Dr. Ammann. The thesis was co-advised by Dr. Gaj and Dr. Kaps. In March 2018, William accepted the tenure-track assistant professor position at Virginia Tech in Blacksburg, VA. (04/25/2018)


CERG Team gave two demos and one poster presentation at HOST 2018

CERG Team, including Abubakr Abdulgadir, Ryan Carter, William Diehl, Raghurama Velagala, Dr. Kaps, and Dr. Gaj, attended the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, held in McLean, VA, on April 30-May 4, 2018. During this conference, our team gave two demos entitled: Flexible, Opensource workBench fOr Side-channel analysis (FOBOS) and eXtended eXternal Benchmarking eXtension (XXBX). Additionally, William Diehl gave the poster presentation entitled "Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers," co-authored with Abubakr Abdulgadir, Farnoud Farahmand, Dr. Kaps, and Dr. Gaj. Finally, Michael Tempelmeier from Technical University of Munich (TUM) gave the talk entitled "The CAESAR-API in the Real World - Towards a Fair Evaluation of Hardware CAESAR Candidates," co-authored with Dr. Kaps. (04/20/2018)


CERG Team attended CBC 2018, PQCrypto 2018, and First PQC Standardization Conference

CERG Team, including Viet Dang, Ahmed Ferozpuri, Duc Nguyen, Dr. Gaj, and Dr. Kaps, attended a sequence of the following three conferences: The Sixth Code-Based Cryptography Workshop, CBC 2018, held on April 5-6, 2018; The Ninth International Conference on Post-Quantum Cryptography, PQCrypto 2018, held on April 9-11, 2018, and First PQC Standardization Conference, held on April 11-13, 2018. All conferences were located in Fort Lauderdale, FL. During the CBC 2018 workshop, Viet Dang gave a talk entitled "Hardware Implementation of the Code-based Key Encapsulation Mechanism using Dyadic GS Codes (DAGS)," co-authored with Dr. Gaj. During the Recent Results Session at the PQCrypto 2018 conference, Dr. Gaj, Ahmed Ferozpuri, and Viet Dang gave three short talks entitled, respectively, "PQC Hardware API & Fair Benchmarking of PQC," "High-Speed HW Implementation of the Multivariate Signature Schemes Unbalanced Oil and Vinegar (UOV), and Rainbow," and "Hardware Implementation of DAGS". (04/14/2018)


Latest publications:

Copyright Notice

The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the caesar lightweight finalists: Acorn vs. Ascon, Cryptology ePrint Archive, number 2019, pages 184, March, 2019 [Bibtex]
  • F. Farahmand, M.U. Sharif, K. Briggs, and K. Gaj, A high-speed constant-time hardware implementation of NTRUEncrypt SVES, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • A. Ferozpuri and K. Gaj, High-speed FPGA implementation of the NIST Round 1 Rainbow signature scheme, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • M. Tempelmeier, J.-P. Kaps, and G. Sigl, Experimental power and performance evaluation of CAESAR hardware finalists, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • G. Banegas, P.S.L.M. Barreto, B.O. Boidje, P.-L. Cayrel, G.N. Dione, K. Gaj, C.T. Gueye, R. Haeussler, J.B. Klamti, O. Ndiaye, D.T. Nguyen, and E. Persichetti, DAGS: Key encapsulation using Dyadic GS codes, Journal of Mathematical Cryptology, volume 12, number 4, pages 221–240, December, 2018 [Bibtex]
  • K. Gaj, Challenges and rewards of implementing and benchmarking Post-Quantum Cryptography in hardware, The 28th ACM Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, ACM, May, 2018 [Bibtex]
  • F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Improved lightweight implementations of CAESAR authenticated ciphers, The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, IEEE, pages 29–36, April, 2018 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, The CAESAR-api in the real world - towards a fair evaluation of hardware CAESAR candidates, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, April, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Side-channel resistant soft core processor for lightweight block ciphers, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • F. Farahmand, A. Ferozpuri, W. Diehl, and K. Gaj, Minerva: Automated hardware optimization tool, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, IEEE, Dec., 2017 [Bibtex]
  • P. Yalla and J.-P. Kaps, Evaluation of CAESAR hardware API for lightweight implementations, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • A. Salman, W. Diehl, and J.-P. Kaps, A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • E. Homsirikamol and K. Gaj, Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, Dec, 2017 [Bibtex]
  • B. Jarvis and K. Gaj, Selection of an error-correcting code for FPGA-based Physical Unclonable Functions, 2017 International Conference on Field-Programmable Technology, FPT 2017, Melbourne, Australia, IEEE, Dec., 2017 [Bibtex]
  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • S. Deshpande and K. Gaj, Analysis and inner-round pipelined implementation of selected parallelizable CAESAR competition candidates, 19th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, Aug., 2017 [Bibtex]
  • B. Habib, J.-P. Kaps, and K. Gaj, Implementation of efficient SR-latch PUF on FPGA and SoC devices, Microprocessors and Microsystems, volume 53, pages 92-105, Aug., 2017 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of selected CAESAR round two authenticated ciphers, Microprocessors and Microsystems, volume 52, pages 202-218, July, 2017 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Microprocessors and Microsystems, volume 51, pages 239-251, June, 2017 [Bibtex]
  • R. Shahid, T. Winograd, and K. Gaj, A generic approach to the development of coprocessors for Elliptic Curve Cryptosystems, 24th Reconfigurable Architectures Workshop, RAW 2017, Orlando, FL, May, 2017 [Bibtex]
  • C. Marchand, L. Bossuet, and K. Gaj, Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes, International Journal of Circuit Theory and Applications, volume 45, pages 274-291, Feb., 2017 [Bibtex]
  • F. Farahmand, E. Homsirikamol, and K. Gaj, A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Dec, 2016 [accepted version, pdf] [Bibtex]
  • E. Homsirikamol and K. Gaj, AEZ: Anything-but EaZy in Hardware, INDOCRYPT 2016, LNCS, Springer, Dec, 2016 [Bibtex]
  • W. Diehl and K. Gaj, Implementation of a Boolean masking scheme for the SCREAM cipher, 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • W. Diehl and K. Gaj, RTL implementations and FPGA benchmarking of three authenticated ciphers competing in CAESAR round two, 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • B. Habib and K. Gaj, A comprehensive set of schemes for PUF response generation, Applied Reconfigurable Computing, Lecture Notes in Computer Science, volume 9625, Springer International Publishing, pages 183–194, March, 2016 [Bibtex] [slides]