Ahmad A Salman


George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
Office: Nguyen Engineering Building, Room 3224
Phone (lab): 703-993-1561
E-Mail: asalman'at'gmu.edu
PGP Key ID: A10F9754
Curriculum Vitae: Ahmad A Salman

Research Interest

  • Partial Dynamic Reconfiguration
  • Wireless Sensor Nodes
  • Hardware/Software Co-Design
  • Hardware Trojans
  • Dynamic Reconfiguration
  • Embedded Systems Design
  • Computer Arithmetic and Cryptographic Implementations

For more information check the research page

Advisor: Dr. Jens-Peter Kaps


Ahmad received his Master's degree in Computer Engineering and the Ph.D. degree in Electrical and Computer Engineering from George Mason University in 2011 and 2017, respectively. He earned his Bachelor's degree from Arab Academy for Science and Technology in Alexandria Egypt in 2002.


  • Implementing Partial dynamic reconfigurable system that controls two SHA-3 Candidates (Blake and JH) modules through Microblaze microprocessor using Xilinx ISE, EDK and Planahead tools
  • Implemented Grain cipher for FPGA using Xilinx ISE tools ciphering/deciphering process was simulated using Modelsim
  • Implementing RSA cipher using Montgomery multipliers (Harris architecture)
  • Simulated the breaking of the Enigma machine code


  • A. Salman, Public key cryptography using hardware/software co-design for the internet of things, ECE Department, George Mason University, Fairfax, Virginia, USA, Aug, 2017, Ph.D. Dissertation [Bibtex]
  • A. Salman, W. Diehl, and J.-P. Kaps, A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun, Hybrid STT-cmos designs for reverse-engineering prevention, ACM/IEEE 53rd Design Automation Conference, DAC 2016, Austin, TX, June 18-22, 2016 [Bibtex]
  • A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig`11, IEEE, pages 242–248, Dec, 2011 [pre-print, pdf] [Bibtex]
  • A. Salman, IPSec implementation in embedded systems for partial reconfigurable platforms, ECE Department, George Mason University, Fairfax, Virginia, USA, May, 2011, Master's Thesis [pdf] [Bibtex]