Shaunak S. Shah


E-Mail: sshahe'at'
Personal Homepage:

Research Interest

  • Cryptographic hardware implementations
  • Side channel analysis
  • Hardware implementations of computer arithmetic.

Advisors: Dr. Jens-Peter Kaps and Dr. David D. Hwang


Shaunak was a Teaching Assistant in the Electrical and Computer Engineering Department at GMU. He completed his M.S. degree in Computer Engineering as part of CERG in May 2010. He received his B.S. degree from K.J.Somaiya College of Engineering, Mumbai, India, in 2006.


  • S. Shah, R. Velegalati, J.-P. Kaps, and D. Hwang, Investigation of DPA resistance of Block RAMs in cryptographic implementations on FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'10, IEEE, pages 274–279, Dec, 2010 [pre-print, pdf] [Bibtex]
  • S. Shah, Investigation of DPA resistance of block RAMs in FPGAs, ECE Department, George Mason University, Fairfax, Virginia, USA, May, 2010, Master's Thesis [pdf] [Bibtex]