Department of Electrical and Computer Engineering George Mason University Volgenau School of Engineering

Publications

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The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • A. Abdulgadir, J.-P. Kaps, and A. Salman, Enhancing information security courses with remotely accessible side-channel analysis setup, Proceedings of the 2022 on Great Lakes Symposium on VLSI, ACM, Irvine, CA, Jun, 2022 [pdf] [Bibtex]
  • A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj, A lightweight implementation of Saber resistant against side-channel attacks, 22nd International Conference on Cryptology in India, Indocrypt 2021, Dec, 2021 [Bibtex]
  • A. Abdulgadir, K. Mohajerani, V. Dang, J.-P. Kaps, and K. Gaj, A lightweight implementation of Saber resistant against side-channel attacks, Oct, 2021, Cryptology ePrint Archive, Paper 2021/1452 [Bibtex]
  • A. Abdulgadir, S. Lin, F. Farahmand, J.-P. Kaps, and K. Gaj, Side-channel resistant implementations of a novel lightweight authenticated cipher with application to hardware security, Proc. Great Lakes Symposium on VLSI, GLSVLSI 2021, pages 229-234, June, 2021 [Bibtex]
  • K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Hardware benchmarking of Round 2 candidates in the NIST lightweight cryptography standardization process, 24th Design, Automation and Test in Europe Conference, DATE 2021, Feb, 2021 [Bibtex]
  • J. Bahrami, V. Dang, A. Abdulgadir, K.N. Khasawneh, J.-P. Kaps, and K. Gaj, Lightweight implementation of the LowMC block cipher protected against side-channel attacks, Proc. 4th ACM Workshop on Attacks and Solutions in Hardware Security, ASHES 2020, pages 45-56, Nov, 2020 [pdf] [Bibtex]
  • A. Abdulgadir, W. Diehl, and J.-P. Kaps, An open-source platform for evaluation of hardware implementations of lightweight authenticated ciphers, 2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, Dec., 2019 [Accepted Version, pdf] [Bibtex]
  • A. Abdulgadir, W. Diehl, and J.-P. Kaps, Flexible, Opensource workBench fOr Side-channel analysis (FOBOS), user guide, v2.0, Cryptographic Engineering Research Group, Dec, 2019 [pdf] [Bibtex]
  • A. Abdulgadir, W. Diehl, and J.-P. Kaps, An open-source platform for evaluating side-channel countermeasures in hardware implementations of lightweight authenticated ciphers, Lightweight Cryptography Workshop 2019, NIST, pages 12, Nov, 2019 [pdf] [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, Cryptology ePrint Archive, number 184, March, 2019 [Bibtex]
  • M. Tempelmeier, J.-P. Kaps, and G. Sigl, Experimental power and performance evaluation of CAESAR hardware finalists, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Face-off between the CAESAR lightweight finalists: ACORN vs. Ascon, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Improved lightweight implementations of CAESAR authenticated ciphers, 2018, Cryptology ePrint Archive, Report 2018/573 [pdf] [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, The CAESAR-api in the real world - towards a fair evaluation of hardware CAESAR candidates, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, Apr, 2018 [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, April, 2018 [Bibtex]
  • M.R. Carter, R. R, J. Pham, and J.-P. Kaps, EXtended eXternal benchmarking eXtension (XXBX), IEEE Hardware Oriented Security and Trust: Hardware Demo, 2018 [Bibtex]
  • A. Abdulgadir, W. Diehl, R. Velegalati, and J.-P. Kaps, Flexible, Opensource workBench fOr Side-channel analysis, IEEE Hardware Oriented Security and Trust: Hardware Demo, 2018 [pdf] [Bibtex]
  • W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj, Comparison of cost of protection against differential power analysis of selected authenticated ciphers, 2018, Cryptology ePrint Archive, Report 2018/341 [pdf] [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs, Computers, volume 7, number 2, Apr, 2018 [Bibtex]
  • F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Improved lightweight implementations of CAESAR authenticated ciphers, The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, IEEE, pages 29–36, April, 2018 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • P. Yalla and J.-P. Kaps, Evaluation of CAESAR hardware API for lightweight implementations, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Side-channel resistant soft core processor for lightweight block ciphers, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • A. Salman, W. Diehl, and J.-P. Kaps, A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj, Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs, International Conference on Field Programmable Technology (FPT 2017), Melbourne, Australia, Dec, 2017 [Bibtex]
  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • B. Habib, J.-P. Kaps, and K. Gaj, Implementation of efficient SR-latch PUF on FPGA and SoC devices, Microprocessors and Microsystems, volume 53, pages 92-105, Aug., 2017 [Bibtex]
  • J.-P. Kaps, EXtended eXternal Benchmarking eXtension (XXBX), Oct., 2016, SPEED-B - Software performance enhancement for encryption and decryption, and benchmarking [pdf] [Bibtex]
  • M. Tempelmeier, F. De, J.-P. Kaps, and G. Sigl, An area-optimized serial implementation of ICEPOLE authenticated encryption schemes, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 49–54, May, 2016 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, Efficient SR-latch PUF, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015, LNCS, volume 9040, Springer, pages 205—216, Apr., 2015 [accepted version, pdf] [Bibtex]
  • J. Pham and J.-P. Kaps, EXtended eXternal Benchmarking eXtension (XXBX), Sep., 2015 [pdf] [Bibtex]
  • B. Habib, K. Gaj, and J.-P. Kaps, FPGA PUF based on programmable LUT delays, 2013 Euromicro Conference on Digital System Design (DSD), pages 697–704, 2013 [accepted version, pdf] [Bibtex]
  • R. Velegalati, K. Shah, and J.-P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, 2013 Euromicro Conference on Digital System Design (DSD), pages 947–954, 2013 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS), June, 2013, Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI 2013 [pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis, May, 2012, Work in Progress (WiP), Third International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2012 [pdf] [Bibtex]
  • C. Wenzel-Benner, J. Gräf, J. Pham, and J.-P. Kaps, XBX benchmarking results January 2012, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • F.K. Gürkaynak, K. Gaj, B. Muheim, E. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASICfor evaluating third round SHA-3 candidates, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [pre-print, pdf] [Bibtex]
  • A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig`11, IEEE, pages 242–248, Dec, 2011 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [pre-print, pdf] [Bibtex]
  • X. Xin, J.-P. Kaps, and K. Gaj, A configurable ring-oscillator-based PUF for Xilinx FPGAs, 14th EUROMICRO Conference on Digital System Design – DSD'11, IEEE, pages 651–657, Aug, 2011 [pre-print, pdf] [Bibtex] Nominated for best paper award.
  • S. Shah, R. Velegalati, J.-P. Kaps, and D. Hwang, Investigation of DPA resistance of Block RAMs in cryptographic implementations on FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'10, IEEE, pages 274–279, Dec, 2010 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic, International Conference on Electronics, Circuits, and Systems, ICECS 2010, IEEE, pages 1251–1254, Dec, 2010 [pre-print, pdf] [Bibtex]
  • K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, and B.Y. Brewster, ATHENa – automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs, 20th International Conference on Field Programmable Logic and Applications - FPL 2010, IEEE, pages 414–421, 2010 [accepted version, pdf] [Bibtex] Winner of the FPL Community Award.
  • J.-P. Kaps and R. Velegalati, DPA resistant AES on FPGA using partial DDL, IEEE Symposium on Field-Programmable Custom Computing Machines – FCCM 2010, IEEE, pages 273–280, May, 2010 [pre-print, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Lightweight cryptography for FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'09, IEEE, pages 225–230, Dec., 2009 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 385–390, Aug, 2009 [, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Compact FPGA implementation of Camellia, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 658–661, Aug., 2009 [pre-print, pdf] [Bibtex]
  • J.-P. Kaps, Chai-tea, cryptographic hardware implementations of xTEA, Progress in Cryptology – INDOCRYPT 2008, Lecture Notes in Computer Science (LNCS), volume 5365, Springer, Heidelberg, pages 363–375, Dec, 2008 [extended version, pdf] [Bibtex]
  • J.-P. Kaps, G. Gaubatz, and B. Sunar, Cryptography on a speck of dust, Computer, volume 40, number 2, pages 38–44, Feb, 2007 [Pre-print, pdf] [Bibtex]
  • J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing, Embedded and Ubiquitous Computing (EUC-06) Workshop Proceedings, Lecture Notes in Computer Science (LNCS), volume 4097, Springer, pages 372–381, Aug, 2006 [expanded version, pdf] [Bibtex]
  • J.-P. Kaps, Cryptography for ultra-low power devices, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 2006, Ph.D. Dissertation [pdf] [Bibtex]
  • J.-P. Kaps, K. Yüksel, and B. Sunar, Energy scalable universal hashing, IEEE Transactions on Computers, volume 54, number 12, pages 1484–1495, Dec, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, E. Öztürk, and B. Sunar, State of the art in ultra-low power public key cryptography for wireless sensor networks, Third IEEE International Conference on Pervasive Computing and Communications Workshops, Workshop on Pervasive Computing and Communications Security–PerSec'05, IEEE Computer Society, pages 146–150, Mar, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, and B. Sunar, Public key cryptography in sensor networks—revisited, 1st European Workshop on Security in Ad-Hoc and Sensor Networks (ESAS 2004), Lecture Notes in Computer Science (LNCS), volume 3313, Springer, Heidelberg, pages 2–18, August, 2004 [pdf] [Bibtex]
  • K. Yüksel, J.-P. Kaps, and B. Sunar, Universal hash functions for emerging ultra-low-power networks, Proceeding of The Communications Networks and Distributed Systems Modeling and Simulation Conference (CNDS), Society for Modeling and Simulation International (SCS), San Diego, CA, January, 2004 [pdf] [Bibtex]
  • J.-P. Kaps and C. Paar, DES auf FPGAs – Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware, Datenschutz und Datensicherheit, volume 23, number 10, Oct, 1999 [pdf] [Bibtex]
  • J.-P. Kaps and C. Paar, Fast DES implementations for FPGAs and its application to a universal key-search machine, Selected Areas in Cryptography, 5th Annual International Workshop, SAC'98, Proceedings, Lecture Notes in Computer Science (LNCS), volume 1556, Queen's University, Kingston, Ontario, Canada, Springer-Verlag, Berlin, pages 234–247, 1999 [, pdf] [Bibtex]
  • J.-P. Kaps, High speed FPGA architectures for the data encryption standard, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 1998, Master's Thesis [, pdf] [Bibtex]