Department of Electrical and Computer Engineering George Mason University Volgenau School of Engineering

Publications

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The research papers below are presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted on third party websites, reproduced, distributed, sold, or licensed without the explicit permission of the copyright holder.

  • B. Habib, K. Gaj, and J.-P. Kaps, FPGA PUF based on programmable LUT delays, 2013 Euromicro Conference on Digital System Design (DSD), pages 697–704, 2013 [accepted version, pdf] [Bibtex]
  • R. Velegalati, K. Shah, and J.-P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, 2013 Euromicro Conference on Digital System Design (DSD), pages 947–954, 2013 [Bibtex]
  • R. Velegalati and J.-P. Kaps, Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS), June, 2013, Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI 2013 [pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis, May, 2012, Work in Progress (WiP), Third International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2012 [pdf] [Bibtex]
  • C. Wenzel-Benner, J. Gr"af, J. Pham, and J.-P. Kaps, XBX benchmarking results January 2012, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • F.K. G"urkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, and J.-P. Kaps, Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates, Mar, 2012 [pdf] [Bibtex] Third {SHA-3} candidate conference
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [pre-print, pdf] [Bibtex]
  • A. Salman, M. Rogawski, and J.-P. Kaps, Efficient hardware accelerator for IPSEC based on partial reconfiguration on Xilinx FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig`11, IEEE, pages 242–248, Dec, 2011 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Improving security of SDDL designs through interleaved placement on Xilinx FPGAs, Field Programmable Logic and Applications, FPL 2011, IEEE, pages 506–511, Sep, 2011 [pre-print, pdf] [Bibtex]
  • X. Xin, J.-P. Kaps, and K. Gaj, A configurable ring-oscillator-based PUF for Xilinx FPGAs, 14th EUROMICRO Conference on Digital System Design – DSD'11, IEEE, pages 651–657, Aug, 2011 [pre-print, pdf] [Bibtex] Nominated for best paper award.
  • S. Shah, R. Velegalati, J.-P. Kaps, and D. Hwang, Investigation of DPA resistance of Block RAMs in cryptographic implementations on FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'10, IEEE, pages 274–279, Dec, 2010 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic, International Conference on Electronics, Circuits, and Systems, ICECS 2010, IEEE, pages 1251–1254, Dec, 2010 [pre-print, pdf] [Bibtex]
  • K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, and B.Y. Brewster, ATHENa – automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs, 20th International Conference on Field Programmable Logic and Applications - FPL 2010, IEEE, pages 414–421, 2010 [accepted version, pdf] [Bibtex] Winner of the FPL Community Award.
  • J.-P. Kaps and R. Velegalati, DPA resistant AES on FPGA using partial DDL, IEEE Symposium on Field-Programmable Custom Computing Machines – FCCM 2010, IEEE, pages 273–280, May, 2010 [pre-print, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Lightweight cryptography for FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'09, IEEE, pages 225–230, Dec., 2009 [pre-print, pdf] [Bibtex]
  • R. Velegalati and J.-P. Kaps, DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 385–390, Aug, 2009 [, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Compact FPGA implementation of Camellia, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 658–661, Aug., 2009 [pre-print, pdf] [Bibtex]
  • J.-P. Kaps, Chai-tea, cryptographic hardware implementations of xTEA, Progress in Cryptology – INDOCRYPT 2008, Lecture Notes in Computer Science (LNCS), volume 5365, Springer, Heidelberg, pages 363–375, Dec, 2008 [extended version, pdf] [Bibtex]
  • J.-P. Kaps, G. Gaubatz, and B. Sunar, Cryptography on a speck of dust, Computer, volume 40, number 2, pages 38–44, Feb, 2007 [Pre-print, pdf] [Bibtex]
  • J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing, Embedded and Ubiquitous Computing (EUC-06) Workshop Proceedings, Lecture Notes in Computer Science (LNCS), volume 4097, Springer, pages 372–381, Aug, 2006 [expanded version, pdf] [Bibtex]
  • J.-P. Kaps, Cryptography for ultra-low power devices, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 2006, Ph.D. Dissertation [pdf] [Bibtex]
  • J.-P. Kaps, K. Yüksel, and B. Sunar, Energy scalable universal hashing, IEEE Transactions on Computers, volume 54, number 12, pages 1484–1495, Dec, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, E. Öztürk, and B. Sunar, State of the art in ultra-low power public key cryptography for wireless sensor networks, Third IEEE International Conference on Pervasive Computing and Communications Workshops, Workshop on Pervasive Computing and Communications Security–PerSec'05, IEEE Computer Society, pages 146–150, Mar, 2005 [pdf] [Bibtex]
  • G. Gaubatz, J.-P. Kaps, and B. Sunar, Public key cryptography in sensor networks—revisited, 1st European Workshop on Security in Ad-Hoc and Sensor Networks (ESAS 2004), Lecture Notes in Computer Science (LNCS), volume 3313, Springer, Heidelberg, pages 2–18, August, 2004 [pdf] [Bibtex]
  • K. Yüksel, J.-P. Kaps, and B. Sunar, Universal hash functions for emerging ultra-low-power networks, Proceeding of The Communications Networks and Distributed Systems Modeling and Simulation Conference (CNDS), Society for Modeling and Simulation International (SCS), San Diego, CA, January, 2004 [pdf] [Bibtex]
  • J.-P. Kaps and C. Paar, DES auf FPGAs – Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware, Datenschutz und Datensicherheit, volume 23, number 10, Oct, 1999 [pdf] [Bibtex]
  • J.-P. Kaps and C. Paar, Fast DES implementations for FPGAs and its application to a universal key-search machine, Selected Areas in Cryptography, 5th Annual International Workshop, SAC'98, Proceedings, Lecture Notes in Computer Science (LNCS), volume 1556, Queen's University, Kingston, Ontario, Canada, Springer-Verlag, Berlin, pages 234–247, 1999 [, pdf] [Bibtex]
  • J.-P. Kaps, High speed FPGA architectures for the data encryption standard, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May, 1998, Master's Thesis [, pdf] [Bibtex]