Details of Result ID 1858

    • Algorithm
      • Transformation Category:  Cryptographic
      • Transformation:  Hash
      • Group:  SHA-3 Round 3
      • Algorithm:  Keccak
      • Hash Size [bits]:  512
      • Message Block Size [bits]:  576
      • Other Parameters:  -
      • Specification:  Keccak_FinalRnd.zip
      • Formula for Message Size After Padding:  -
    • Design
      • Design ID:  263
      • Primary Optimization Target:  Throughput/Area
      • Secondary Optimization Target:  Throughput
      • Architecture Type:  Pipelined x2-PPL2
      • Description Language:  VHDL
      • Use of Megafunctions or Primitives:  No
      • List of Megafunctions or Primitives:  -
      • Maximum Number of Streams Processed in Parallel:  2
      • Number of Clock Cycles per Message Block in a Long Message:  24
      • Datapath Width [bits]:  1,600
      • Padding:  Yes
      • Minimum Message Unit:  1 byte
      • Input Bus Width [bits]:  128
      • Output Bus Width [bits]:  64
      • Implementation URL:  index.php?id=source_codes
      • Shared I/O Bus:  No
      • Throughput Formula:  1152/(24*T)
      • Execution Time Formula:  3+24*N+8
      • Source Available:  Yes
      • Source Code Files:  link
      • Design Entry Date:  2012-02-16
      • Design Modify Date:  2012-04-10
      • Design Name:  Keccak_x2_PPL2 (512) Pad SHA3C3
      • Comments:  -
    • Platform
      • Device Vendor:  Altera
      • Family:  Stratix IV GX
      • Device:  ep4sgx70hf35c2
    • Timing
      • Throughput [Mbits/s]:  12,490
      • Requested Synthesis Clock Frequency [MHz]:  -
      • Synthesis Clock Frequency [MHz]:  -
      • Requested Implementation Clock Frequency [MHz]:  -
      • Implementation Clock Frequency [MHz]:  260.210
      • Throughput/ALUTs [(Mbits/s)/ALUTs]:  1.898
    • Resource Utilization
      • ALUTs:  6,580
      • Flip Flops:  5,825
      • DSPs:  0
      • Memory Bits:  0
    • Power and Energy Consumption
      • Estimated Power [mW]:  -
      • Estimated Dynamic Power [mW]:  -
      • Estimated Static Power [mW]:  -
      • Estimated Energy/Bit [mJ/Gbit]:  -
      • Operating Conditions used for Estimation (V, Temp, Etc):  -
      • Measured Power [mW]:  -
      • Measured Dynamic Power [mW]:  -
      • Measured Static Power [mW]:  -
      • Measured Energy/Bit [mJ/Gbit]:  -
      • Operating Conditions used for Measurement (V, Temp, Etc):  -
    • Tool Information
      • Synthesis Tool:  Quartus II 32-bit
      • Synthesis Tool Version:  11.1
      • Command Line Synthesis Tool Options:  -
      • QSF Script Synthesis Tool Options:  AUTO_DSP_RECOGNITION OFF
        AUTO_RAM_RECOGNITION OFF
        AUTO_ROM_RECOGNITION OFF
        AUTO_SHIFT_REGISTER_RECOGNITION OFF
        MAX_RAM_BLOCKS_M4K 0
        MAX_RAM_BLOCKS_M512 0
        MAX_RAM_BLOCKS_MRAM 0
        set_parameter -name HS "512"
        set_parameter -name PPL "2"
        set_parameter -name UF "2"
      • Implementation Tool:  Quartus II 32-bit
      • Implementation Tool Version:  11.1
      • Implementation Tool Options:  --SEED=2001 --ONE_FIT_ATTEMPT=ON --PACK_REGISTER=MINIMIZE_AREA --EFFORT=STANDARD
    • Credits
      • Primary Designer Name(s):  Marcin Rogawski
      • Primary Designer Email(s):  mrogawsk@gmu.edu
      • Co-designer Name(s):  Ekawat Homsirikamol, Kris Gaj
      • Co-designer Email(s):  ehomsiri@gmu.edu, kgaj@gmu.edu
      • Primary Designer Affiliation:  CERG @ GMU
      • Co-Designer Affiliation:  CERG @ GMU
    • Other
      • Result Replication Files:  link
      • Result Entry Date:  2012-02-17
      • Result Modify Date:  2012-02-17
      • Design Entered By:  ice
      • Hidden:  No