Protected Hardware Implementations of LWC Finalists

 

No. LWC Candidates Team HDL No. of variants Protection Method Protection Order Initial Evaluation Availability License Primary Hardware Designers Academic Advisors / Program Managers
1 ISAP Institute of Applied Information Processing and Communications (IAIK), Graz University of Technology, Austria VHDL 7 Mode-level robustness against physical attacks N/A analytical GitHub GPL-3.0 Robert Primas Stefan Mangard
2 Ascon, Elephant, GIFT-COFB, ISAP, PHOTON-Beetle, Romulus, SPARKLE, TinyJAMBU, Xoodyak Ruhr-University Bochum, Germany Verilog & VHDL Ascon, Xoodyak: 6
Others: 3
HPC2 1, 2, 3 evaluation of the robust probing security of the implementations GitHub GPL-3.0 Nicolai Mueller Amir Moradi
3 Elephant, TinyJAMBU, Xoodyak, Cryptographic Engineering Research Group (CERG), George Mason University, USA VHDL 1 DOM 1 t-test TinyJAMBU: GitHub; Elephant, Xoodyak: Per request GPL-3.0 Elephant: Richard Haeussler
TinyJAMBU: Sammy Lin & Abubakr Abdulgadir
Xoodyak: Abubakr Abdulgadir & Richard Haeussler;
Jens-Peter Kaps & Kris Gaj
4 Ascon Institute of Applied Information Processing and Communications (IAIK), Graz University of Technology, Austria VHDL 1 DOM 1, 2 formal verification of the masked implementation of Ascon-p in the glitch-extended probing model using COCO Per request GPL-3.0 Robert Primas & Rishub Nagpal Stefan Mangard
5 Xoodyak Hardware Security and Cryptographic Processor Lab, Tsinghua University, Beijing, China Verilog & VHDL 2 DOM, TI 1 t-test GitHub GPL-3.0 Shuohang Peng & Shuying Yin & Cankun Zhao Leibo Liu & Bohan Yang & Wenping Zhu

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