FPGA Hash Function Results Table

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Compare SelectedSHA-3 Round 3SHA-3 Round 3 & SHA-2SHA-3 Round 2SHA-3 Round 2 & SHA-2

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Result ID Algorithm
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Hash Size [bits] Primary Opt Target Arch Type Max #Streams Padding Family TP [Mbits/s] Impl Freq [MHz] CLB Slices LEs ALUTs Estimated Energy/Bit [mJ/Gbit] Measured Energy/Bit [mJ/Gbit] Synth Tool Primary Designer Affiliation Result Modify Date

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