Details of Result ID 836

    • Algorithm
      • IV or Nonce Size [bits]:  128
      • Transformation Category:  Cryptographic
      • Transformation:  Authenticated Cipher
      • Group:  caesar3r3lw
      • Algorithm:  acorn128v3
      • Offline:  No
      • Two-Pass:  No
      • Associated Data Support:  -
      • Key Size [bits]:  128
      • Tag Size [bits]:  128
      • Secret Message Number:  -
      • Secret Message Number Size [bits]:  -
      • Message Block Size [bits]:  32
      • Other Parameters:  -
      • Specification:  -
      • Formula for Message Size After Padding:  -
    • Design
      • Design ID:  179
      • Implementation Approach:  RTL
      • Hardware API:  CAESAR Hardware API v1
      • Log_2(Max Length) rounded up:  -
      • Primary Optimization Target:  Throughput/Area
      • Secondary Optimization Target:  -
      • Architecture Type:  32-bit
      • Description Language:  VHDL
      • Use of Megafunctions or Primitives:  No
      • List of Megafunctions or Primitives:  -
      • Maximum Number of Streams Processed in Parallel:  1
      • Number of Clock Cycles per Message Block in a Long Message:  -
      • Datapath Width [bits]:  -
      • Padding:  Yes
      • Minimum Message Unit:  -
      • Input Bus Width [bits]:  32
      • Output Bus Width [bits]:  32
      • Implementation URL:  -
      • Shared I/O Bus:  Yes
      • Encryption/Auth Throughput Formula:  32/T
      • Decryption/Auth Throughput Formula:  32/T
      • Authentication-Only Throughput Formula:  32/T
      • Key Scheduling Time Formula:  -
      • Encryption/Authentication Time Formula:  -
      • Dec/Authentication Time Formula:  -
      • Authentication-Only Time Formula:  -
      • Interface/Protocol Specification:  -
      • Source Available:  No
      • Source Code Files:  -
      • Design Entry Date:  2017-08-12
      • Design Modify Date:  2017-08-14
      • Design Name:  Acorn [CCRG NTU Singapore] [2017-07-15] [v1-2] [32-bit]
      • Comments:  -
    • Platform
      • Device Vendor:  Altera
      • Family:  Stratix IV
      • Device:  ep4se530h35c2
    • Resource Utilization
      • ALUTs:  1,097
      • ALMs:  787
      • Flip Flops:  -
      • DSPs:  0
      • Memory Bits:  0
    • Timing
      • Implementation Clock Frequency [MHz]:  336.6
      • Encryption/Authentication Throughput [Mbits/s]:  10,771
      • Decryption/Authentication Throughput [Mbits/s]:  10,771
      • Authentication-Only Throughput [Mbits/s]:  10,771
      • Synthesis Clock Frequency [MHz]:  -
      • Key Scheduling Time [ns]:  -
      • Requested Synthesis Clock Frequency [MHz]:  -
      • Requested Implementation Clock Frequency [MHz]:  -
      • (Encryption/Authentication Throughput)/ALUT [(Mbits/s)/ALUT]:  9.818
      • (Decryption/Authentication Throughput)/ALUT [(Mbits/s)/ALUT]:  9.818
      • (Auth-Only Throughput)/ALUT [(Mbits/s)/ALUT]:  9.818
    • Power and Energy Consumption
      • Estimated Power [mW]:  -
      • Estimated Dynamic Power [mW]:  -
      • Estimated Static Power [mW]:  -
      • Estimated Energy/Bit [mJ/Gbit]:  -
      • Operating Conditions used for Estimation (V, Temp, Etc):  -
      • Measured Power [mW]:  -
      • Measured Dynamic Power [mW]:  -
      • Measured Static Power [mW]:  -
      • Measured Energy/Bit [mJ/Gbit]:  -
      • Operating Conditions used for Measurement (V, Temp, Etc):  -
    • Tool Information
      • High Level Synthesis Tool:  -
      • High Level Synthesis Tool Input Language:  -
      • High Level Synthesis Tool Output Language:  -
      • High Level Synthesis Tool Version:  -
      • High Level Synthesis Tool Options:  -
      • Synthesis Tool:  Quartus Prime (ATHENa)
      • Synthesis Tool Version:  16.0.0
      • QSF Script Synthesis Tool Options:  -
      • Command Line Synthesis Tool Options:  -
      • Implementation Tool:  Quartus Prime (ATHENa)
      • Implementation Tool Version:  16.0.0
      • Implementation Tool Options:  -
    • Credits
      • Primary Designer Name(s):  Tao Huang
      • Primary Designer Email(s):  huangtaochn@gmail.com
      • Co-designer Name(s):  Hongjun Wu
      • Co-designer Email(s):  wuhongjun@gmail.com
      • Primary Designer Affiliation:  CCRG, NTU Singapore
      • Co-Designer Affiliation:  CCRG, NTU Singapore
    • Other
      • Result Replication Files:  -
      • Result Entry Date:  2017-08-14
      • Result Modify Date:  2017-08-14
      • Design Entered By:  CERG
      • Hidden:  No