// ============================================================================= // Copyright © 2019 by Cryptographic Engineering Research Group (CERG), // ECE Department, George Mason University // Fairfax, VA, U.S.A. // Author: Farnoud Farahmand // ============================================================================= #include "xil_types.h" #include "xstatus.h" #define clk_wiz_S_AXI_Software_Reset_OFFSET 0x0 #define clk_wiz_S_AXI_SLV_Status_Reg_OFFSET 0x04 #define clk_wiz_S_AXI_clk_Conf_Reg0_OFFSET 0x200 #define clk_wiz_S_AXI_clk_Conf_Reg1_OFFSET 0x204 #define clk_wiz_S_AXI_clk_Conf_Reg2_OFFSET 0x208 #define clk_wiz_S_AXI_clk_Conf_Reg3_OFFSET 0x20C #define clk_wiz_S_AXI_clk_Conf_Reg4_OFFSET 0x210 #define clk_wiz_S_AXI_clk_Conf_Reg5_OFFSET 0x214 #define clk_wiz_S_AXI_clk_Conf_Reg6_OFFSET 0x218 #define clk_wiz_S_AXI_clk_Conf_Reg7_OFFSET 0x21C #define clk_wiz_S_AXI_clk_Conf_Reg8_OFFSET 0x220 #define clk_wiz_S_AXI_clk_Conf_Reg9_OFFSET 0x224 #define clk_wiz_S_AXI_clk_Conf_Reg10_OFFSET 0x228 #define clk_wiz_S_AXI_clk_Conf_Reg11_OFFSET 0x22C #define clk_wiz_S_AXI_clk_Conf_Reg12_OFFSET 0x230 #define clk_wiz_S_AXI_clk_Conf_Reg13_OFFSET 0x234 #define clk_wiz_S_AXI_clk_Conf_Reg14_OFFSET 0x238 #define clk_wiz_S_AXI_clk_Conf_Reg15_OFFSET 0x23C #define clk_wiz_S_AXI_clk_Conf_Reg16_OFFSET 0x240 #define clk_wiz_S_AXI_clk_Conf_Reg17_OFFSET 0x244 #define clk_wiz_S_AXI_clk_Conf_Reg18_OFFSET 0x248 #define clk_wiz_S_AXI_clk_Conf_Reg19_OFFSET 0x24C #define clk_wiz_S_AXI_clk_Conf_Reg20_OFFSET 0x250 #define clk_wiz_S_AXI_clk_Conf_Reg21_OFFSET 0x254 #define clk_wiz_S_AXI_clk_Conf_Reg22_OFFSET 0x258 #define clk_wiz_S_AXI_clk_Conf_Reg23_OFFSET 0x25C #define clk_wiz_mWriteReg(BaseAddress, RegOffset, Data) \ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) #define clk_wiz_mReadReg(BaseAddress, RegOffset) \ Xil_In32((BaseAddress) + (RegOffset)) void UpdateFrequency (float accel_freq);