From f4c488439bcfd055bdb73eb0da6bb53a3e507a7f Mon Sep 17 00:00:00 2001 From: farnoud Date: Sat, 28 Sep 2019 14:54:35 -0700 Subject: [PATCH] updated README --- README | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/README b/README index 4b5be51..79c7916 100644 --- a/README +++ b/README @@ -58,3 +58,26 @@ well as the achieved speed-up. You can also set the "POLY_MUL_EXE" parameter to 1 in the DMA_Transfer_def.h to print out the execution time of hardware accelerator only. + +This platform has been used for generating results reported in the following +publications: + +- F. Farahmand, V. Dang, M. Andrzejczak, K. Gaj, “Implementing and Benchmarking + Seven Round 2 Lattice-Based Key Encapsulation Mechanisms Using a + Software/Hardware Codesign Approach”. In NIST Second PQC Standardization + Conference, Santa Barbara, USA, Aug 2019. + https://csrc.nist.gov/CSRC/media/Events/Second-PQC-Standardization-Conference/ + documents/accepted-papers/gaj-implementing-benchmarking.pdf + +- F. Farahmand, V. Dang, D. Nguyen, and K. Gaj, “Evaluating the Potential for + Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using + Software/Hardware Codesign”. In: 10th International Conference on Post-Quantum + Cryptography, PQCrypto 2019. LNCS. Chongqing, China: Springer, May 2019. + https://link.springer.com/chapter/10.1007/978-3-030-25510-7_2 + +- F. Farahmand, D. Nguyen, V. Dang, A. Ferozpuri, and K. Gaj, “Software/Hardware + Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using + High-Level Synthesis and Register-Transfer Level Design Methodologies”, In + 29th International Conference on Field Programmable Logic and Applications + (FPL), Barcelona, Spain, Sep. 9-13, 2019. + https://par.nsf.gov/biblio/10108524 -- libgit2 0.26.0