vrl.vhd 2.63 KB
Newer Older
Viet Dang committed
1 2 3 4 5 6
-- =============================================================================
-- Copyright © 2018-2019 by Cryptographic Engineering Research Group (CERG),
-- ECE Department, George Mason University
-- Fairfax, VA, U.S.A.
-- Author: Malik Umar Sharif, Kevin Briggs, Viet B. Dang
-- =============================================================================
Farnoud Farahmand committed
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

library work;
use work.sha2_pkg.all;
use work.sha3_pkg.all;
use work.ntru_pkg.all;

entity vrl is	-- variable rotate left
generic
(
	PIPE_N  : std_logic_vector := "111";
	NUM  : integer := 8;
	NUMWIDTH  : integer := 1
);
port
(
	-- input
	clk : in std_logic;
	rst : in std_logic;
	A 	: in std_logic_vector(NUM*NUMWIDTH-1 downto 0);
	B 	: in std_logic_vector(log2ceil(NUM)-1 downto 0);
	-- output
	C 	: out std_logic_vector(NUM*NUMWIDTH-1 downto 0)
);
end vrl;

-- ==========================================================================
architecture arch of vrl is

    constant ROTWIDTH : integer := log2ceil(NUM);

	type array1 is array (0 to ROTWIDTH) of std_logic_vector(NUM*NUMWIDTH-1 downto 0);
	type array2 is array (0 to ROTWIDTH-1) of std_logic_vector(NUM*NUMWIDTH-1 downto 0);
	type array3 is array (0 to ROTWIDTH) of std_logic_vector(log2ceil(NUM)-1 downto 0);
	signal Al : array1;
	signal Ar : array2;

    signal Bp: array3;
    
	type Al_t_array is array (1 to ROTWIDTH) of std_logic_vector(NUM*NUMWIDTH-1 downto 0);
	signal Al_t : Al_t_array;

	type PIPE_i_array is array (0 to ROTWIDTH-1) of integer;

begin
    Al(0) <= A;
    Bp(0) <= B;
    G: for i in 0 to ROTWIDTH-1 generate

        ROT_I : entity work.fixed_rotator(left) generic map (WIDTH => NUM*NUMWIDTH, ROT => NUMWIDTH*(2**i))
            port map (a => Al(i), y => Ar(i));
--        SHIFT_I: entity work.fixed_rotator_right(arch) generic map (WIDTH => NUM*NUMWIDTH, ROT => NUMWIDTH*(2**I))
--			port map ( a => Al(i), y => Ar(i) );
        Al_t(i+1) <= Al(i) when Bp(i)(i) = '0' else Ar(i);

		PIPE_i_0: if (PIPE_N(i) = '0') generate
			Al(i+1) <= Al_t(i+1);
			Bp(i+1) <= Bp(i);
		end generate;

		PIPE_i_1: if (PIPE_N(i) = '1') generate
			reg_i : entity work.regn (pos_edge) generic map (N => NUM*NUMWIDTH, init => ZEROs)
				port map(clk => clk, rst => rst, en => '1', input => Al_t(i+1), output => Al(i+1));
		    reg_b: entity work.regn (pos_edge) generic map(N => log2ceil(NUM), init => ZEROs)
		        port map(clk => clk, rst => rst, en => '1', input => Bp(i), output => Bp(i+1));
		end generate;

    end generate;

	C <= Al(ROTWIDTH);

end arch;
-- ==========================================================================