Details of Result ID 1246
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Algorithm
- Transformation Category: Cryptographic
- Transformation: Hash
- Group: SHA-3 Round 3
- Algorithm: JH
- Hash Size [bits]: 256
- Message Block Size [bits]: 512
- Other Parameters: -
- Specification: JH_FinalRnd.zip
- Formula for Message Size After Padding: -
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Design
- Design ID: 113
- Primary Optimization Target: Throughput/Area
- Description Language: VHDL
- Secondary Optimization Target: Throughput
- Architecture Type: Basic Iterative
- Datapath Width [bits]: 512
- Padding: No
- Minimum Message Unit: -
- Input Bus Width [bits]: 64
- Output Bus Width [bits]: 64
- Implementation URL: -
- Shared I/O Bus: No
- Throughput Formula: 512/(43*T)
- Execution Time Formula: -
- Source Available: No
- Source Code Files: -
- Design Entry Date: 2011-09-26
- Design Modify Date: 2011-09-26
- Design Name: JH_x1 (OTF) (256)
- Comments: -
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Platform
- Device Vendor: Altera
- Family: Stratix III
- Device: ep3sl50f780c2
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Timing
- Requested Synthesis Clock Frequency [MHz]: -
- Synthesis Clock Frequency [MHz]: -
- Requested Implementation Clock Frequency [MHz]: -
- Implementation Clock Frequency [MHz]: 422.300
- Throughput [Mbits/s]: 5,028
- Throughput/ALUTs [(Mbits/s)/ALUTs]: 1.488
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Resource Utilization
- ALUTs: 3,380
- Flip Flops: 2,616
- DSPs: 0
- Memory Bits: 0
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Tool Information
- Synthesis Tool: Quartus II
- Synthesis Tool Version: 10.1
- Command Line Synthesis Tool Options: -
- QSF Script Synthesis Tool Options: -
- Implementation Tool: Quartus II
- Implementation Tool Version: 10.1
- Implementation Tool Options: --SEED=8001 --ONE_FIT_ATTEMPT=ON --PACK_REGISTER=MINIMIZE_AREA --EFFORT=STANDARD
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Credits
- Primary Designer Name(s): Ekawat Homsirikamol
- Primary Designer Email(s): ehomsiri@gmu.edu
- Co-designer Name(s): Marcin Rogawski, Kris Gaj
- Co-designer Email(s): mrogawsk@gmu.edu, kgaj@gmu.edu
- Primary Designer Affiliation: CERG @ GMU
- Co-Designer Affiliation: CERG @ GMU
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Other
- Result Replication Files: link
- Result Entry Date: 2011-09-26
- Result Modify Date: 2011-09-26
- Hidden: No