Details of Result ID 1586

    • Algorithm
      • Transformation Category:  Cryptographic
      • Transformation:  Hash
      • Group:  SHA-3 Round 2
      • Algorithm:  Keccak
      • Hash Size [bits]:  256
      • Message Block Size [bits]:  1,088
      • Other Parameters:  -
      • Specification:  Keccak_Round2.zip
      • Formula for Message Size After Padding:  -
    • Design
      • Design ID:  198
      • Primary Optimization Target:  Throughput
      • Description Language:  VHDL
      • Secondary Optimization Target:  -
      • Architecture Type:  Basic Iterative
      • Maximum Number of Streams Processed in Parallel:  1
      • Number of Clock Cycles per Message Block in a Long Message:  24
      • Datapath Width [bits]:  -
      • Padding:  No
      • Minimum Message Unit:  -
      • Input Bus Width [bits]:  1,088
      • Output Bus Width [bits]:  -
      • Implementation URL:  index_r2.html
      • Shared I/O Bus:  No
      • Throughput Formula:  1088/(T*24)
      • Execution Time Formula:  -
      • Source Available:  No
      • Source Code Files:  -
      • Design Entry Date:  2012-11-18
      • Design Modify Date:  2012-11-18
      • Design Name:  Keccak-256
      • Publication URL:  -
      • Comments:  -
    • Platform
      • Library Vendors:  Faraday
      • Library Names:  fsd0a_a_2009Q2v2.0 RVT standard cell library
      • Target Technology [nm]:  90
      • Die Size [mm²]:  -
      • Technology Comments:  -
      • Semiconductor Foundry:  -
      • Status of Chip:  Fabricated
    • Timing
      • Requested Post-Synthesis Clock Frequency [MHz]:  -
      • Post-Synthesis Clock Frequency [MHz]:  -
      • Post-Synthesis Throughput [Mbits/s]:  -
      • Post-Synthesis Throughput/Area [(Mbits/s)/kGEs]:  -
      • Requested Post-Layout Clock Frequency [MHz]:  441.000
      • Post-Layout Clock Frequency [MHz]:  949.000
      • Post-Layout Throughput [Mbits/s]:  43,011
      • Post-Layout Throughput/Area [(Mbits/s)/kGEs]:  860.220
      • Measured Clock Frequency [MHz]:  -
      • Measured Throughput [Mbits/s]:  -
      • Measured Throughput/Area [(Mbits/s)/kGEs]:  -
      • Timing Result Comments (Operating Conditions: temperature, voltage, etc.):  -
    • Resource Utilization
      • Post-Synthesis Area [μm²]:  -
      • Post-Synthesis Area [kGE]:  -
      • Post-Layout Area [μm²]:  -
      • Post-Layout Area [kGE]:  50
    • Power and Energy Consumption [Condition 1]
      • Post-Synthesis Power [mW]:  -
      • Post-Synthesis Static Power [mW]:  -
      • Post-Synthesis Dynamic Power [mW]:  -
      • Post-Layout Power [mW]:  -
      • Post-Layout Dynamic Power [mW]:  -
      • Post-Layout Static Power [mW]:  -
      • Post-Layout Energy/Bit [mJ/Gbit]:  -
      • Post-Layout Operating Conditions (V, Temp, etc):  -
      • Measured Power [mW]:  -
      • Measured Static Power [mW]:  -
      • Measured Dynamic Power [mW]:  -
      • Measured Energy/Bit [mJ/Gbit]:  -
      • Measurement Operating Conditions (V, Temp, etc):  -
    • Power and Energy Consumption [Condition 2]
      • Post-Synthesis Power [mW]:  -
      • Post-Synthesis Static Power [mW]:  -
      • Post-Synthesis Dynamic Power [mW]:  -
      • Post-Layout Power [mW]:  -
      • Post-Layout Dynamic Power [mW]:  -
      • Post-Layout Static Power [mW]:  -
      • Post-Layout Energy/Bit [mJ/Gbit]:  -
      • Post-Layout Operating Conditions (V, Temp, etc):  -
      • Measured Power [mW]:  -
      • Measured Static Power [mW]:  -
      • Measured Dynamic Power [mW]:  -
      • Measured Energy/Bit [mJ/Gbit]:  -
      • Measurement Operating Conditions (V, Temp, etc):  -
    • Power and Energy Consumption [Condition 3]
      • Post-Synthesis Power [mW]:  -
      • Post-Synthesis Static Power [mW]:  -
      • Post-Synthesis Dynamic Power [mW]:  -
      • Post-Layout Power [mW]:  -
      • Post-Layout Dynamic Power [mW]:  -
      • Post-Layout Static Power [mW]:  -
      • Post-Layout Energy/Bit [mJ/Gbit]:  -
      • Post-Layout Operating Conditions (V, Temp, etc):  -
      • Measured Power [mW]:  -
      • Measured Static Power [mW]:  -
      • Measured Dynamic Power [mW]:  -
      • Measured Energy/Bit [mJ/Gbit]:  -
      • Measurement Operating Conditions (V, Temp, etc):  -
    • Tools Information
      • Synthesis Tools Vendor:  Synopsys
      • Synthesis Tool:  Synopsys Design Vision
      • Synthesis Tools Version:  2009.06
      • Synthesis Scripts:  -
      • Backend Tools Vendor:  Cadence
      • Backend Tool:  Cadence Design Systems
      • Backend Tools Version:  Velocity-9.1
      • Backend Scripts:  -
    • Credits
      • Primary Designer Name(s):  Luca Henzen
      • Primary Designer Email(s):  henzen@iis.ee.ethz.ch
      • Co-designer Name(s):  Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi,Martin Zoller, Frank K. Gürkaynak
      • Co-designer Email(s):  {gpietro,pguillet,penrico,mzoller}@ee.ethz.ch, mailto:kgf@ee.ethz.ch
      • Primary Designer Affiliation:  ETH Zurich
      • Co-Designer Affiliation:  ETH Zurich
    • Other
      • Result Replication Files:  -
      • Result Entry Date:  2012-11-18
      • Result Modify Date:  2012-11-18
      • Design Entered By:  kgf
      • Hidden:  No